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[131.252.210.177]) by mx.google.com with ESMTPS id o4-v6si2284038plk.582.2018.02.06.01.36.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Feb 2018 01:36:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aggrhEaB; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F8286E3D1; Tue, 6 Feb 2018 09:35:54 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id AE7766E3CF for ; Tue, 6 Feb 2018 09:35:52 +0000 (UTC) Received: by mail-lf0-x244.google.com with SMTP id f136so1743727lff.8 for ; Tue, 06 Feb 2018 01:35:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7myVeNaubicFvVaANhnaVp2sPrpGuGLpcgezpNQhWBM=; b=aggrhEaBbxjgYS5wIFY3LvWJm4TXHnq/wf0+pYAzpsv6JmgeP/Tqk3D1laGqUbHzRp c+sB0/Va7Nv+5bkRf8JiiTX40M8jhlGJmqMxS9qmGhGKBXurN/7wHvrLR5xAwykeRlYp Z6A4GdFMYCJvwxFQMAITQD/tYnCTSwJUu6GE4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7myVeNaubicFvVaANhnaVp2sPrpGuGLpcgezpNQhWBM=; b=lc7fi1vNZSy1pFJ95wn725GBbA/IRJ+hikZZ3ruvuLZ+JzQXcJFJO6fTPVeBSYqHaM saftyZPzDP8MW2pszEV9GXbj0e6V0TgzwjtE7LqEowSi8B2mDrdocwvk/MZwqzcOCXYm igY/R5Ur6d4Lp2K5aAPzLNDIKgn7sqVJb5KT0I6d7Ln+YD9r+L96z/LuzYLaAZJql9NI 8nHqWYHYJ/rwvC/EcvHM6m1y23+0pwsBpyczOK8eraZQ0nlvrnCy5fxTI6lw8LbFt+5V CdRed3MwAm7fq+ASuNK19FbSoxU0WBGVbl4Gu6OelaOxb3C1GFMheXpXjgNXxTII7lEo +H+Q== X-Gm-Message-State: APf1xPDIMVYO7KtrbLmSoe/3C1aE/3lABOWdGTTXZtXRL+49mnHLFKTq GzbQlPIRg3d7e0j+Zdzkt64dYrNxqv0= X-Received: by 10.25.81.13 with SMTP id f13mr1270547lfb.50.1517909750926; Tue, 06 Feb 2018 01:35:50 -0800 (PST) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id m129sm2253675lfg.75.2018.02.06.01.35.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Feb 2018 01:35:50 -0800 (PST) From: Linus Walleij To: Daniel Vetter , Jani Nikula , Sean Paul , Eric Anholt Subject: [PATCH 3/5 v3] drm/pl111: Support variants with broken clock divider Date: Tue, 6 Feb 2018 10:35:38 +0100 Message-Id: <20180206093540.8147-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180206093540.8147-1-linus.walleij@linaro.org> References: <20180206093540.8147-1-linus.walleij@linaro.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The early Integrator CLCD synthesized in the Integrator CP and IM-PD1 FPGAs are broken: their clock dividers do not work properly. Support disabling the clock divider and drive the clock directly from the parent under these circumstances. Reviewed-by: Eric Anholt Signed-off-by: Linus Walleij --- ChangeLog ->v3: - Collect Eric's Review tag. --- drivers/gpu/drm/pl111/pl111_display.c | 8 ++++++++ drivers/gpu/drm/pl111/pl111_drm.h | 3 +++ drivers/gpu/drm/pl111/pl111_versatile.c | 1 + 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c index 55ada00ec974..4d4e38b4c9d5 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -138,6 +138,9 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe, tim2 = readl(priv->regs + CLCD_TIM2); tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK); + if (priv->variant->broken_clockdivider) + tim2 |= TIM2_BCD; + if (mode->flags & DRM_MODE_FLAG_NHSYNC) tim2 |= TIM2_IHS; @@ -455,6 +458,11 @@ pl111_init_clock_divider(struct drm_device *drm) dev_err(drm->dev, "CLCD: unable to get clcdclk.\n"); return PTR_ERR(parent); } + /* If the clock divider is broken, use the parent directly */ + if (priv->variant->broken_clockdivider) { + priv->clk = parent; + return 0; + } parent_name = __clk_get_name(parent); spin_lock_init(&priv->tim2_lock); diff --git a/drivers/gpu/drm/pl111/pl111_drm.h b/drivers/gpu/drm/pl111/pl111_drm.h index c2f410f0b12e..f75c5d4645b2 100644 --- a/drivers/gpu/drm/pl111/pl111_drm.h +++ b/drivers/gpu/drm/pl111/pl111_drm.h @@ -38,6 +38,8 @@ struct drm_minor; * @is_pl110: this is the early PL110 variant * @external_bgr: this is the Versatile Pl110 variant with external * BGR/RGB routing + * @broken_clockdivider: the clock divider is broken and we need to + * use the supplied clock directly * @formats: array of supported pixel formats on this variant * @nformats: the length of the array of supported pixel formats */ @@ -45,6 +47,7 @@ struct pl111_variant_data { const char *name; bool is_pl110; bool external_bgr; + bool broken_clockdivider; const u32 *formats; unsigned int nformats; }; diff --git a/drivers/gpu/drm/pl111/pl111_versatile.c b/drivers/gpu/drm/pl111/pl111_versatile.c index ec05c7e5319b..93cf2d82074b 100644 --- a/drivers/gpu/drm/pl111/pl111_versatile.c +++ b/drivers/gpu/drm/pl111/pl111_versatile.c @@ -237,6 +237,7 @@ static const u32 pl110_versatile_pixel_formats[] = { static const struct pl111_variant_data pl110_integrator = { .name = "PL110 Integrator", .is_pl110 = true, + .broken_clockdivider = true, .formats = pl110_integrator_pixel_formats, .nformats = ARRAY_SIZE(pl110_integrator_pixel_formats), };