From patchwork Thu Feb 8 19:21:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 127740 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1796973ljc; Thu, 8 Feb 2018 11:28:58 -0800 (PST) X-Google-Smtp-Source: AH8x224NF9GK5X4qxgMChVpK04YzSly8KNO3ulIzGTlZZubUYJ6uTJ+GpCHbuswnPGG5ynPMke2A X-Received: by 10.36.190.4 with SMTP id i4mr346753itf.20.1518118138840; Thu, 08 Feb 2018 11:28:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518118138; cv=none; d=google.com; s=arc-20160816; b=B7yqRaEOoT4egUx5tDdrfIe/ORzQ/gAP15piX9io1Zx0Z0xOlHBaThI41DcRT3R+Be MDPk8BjkY7r71ZFSycZtpMrDKOWInhzpz2ogP3PEqBQshhLRqlzOMLfW6gOG6o1olPys awc1WB0fe7z4AmkGuZsWQ5+avD4zj90N1krpCGrukM3IfIIY7+uJoT0Xgh94YztLaM86 jEc++yKfCOIxfwT1L4x2wln4FV3TTy25aMXlI/ikQBGhEhNGnR8Zc1rl/OcYgpR3Ltsy I1ZzTeOwsbOz/Yrg6DN/OY+suGu0ipYGvyj2C7TWFI/EWOtZbpvX4LAt7NZGuyt0VgW9 KV+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=RbgpMK4oPVMVlrn9q/08wx2jZAC/Wap3/PtHoTQCp1k=; b=noSRYTR9lMnHNeu7ck6KNXYjqX9r9k8wNi3Ar+qGEF9Lc3Ha19vXHIl7ra2OfooFuE d0EqAHc6COxQN1wrijAHulidCaiNEAtRMopgXl9FkyEKtAPqnPrQPXH/4yu83ndszQx8 +9biPWa1WdmsbdJ9TBwZqsep0oXQE5HQt5qt6p+Wz5jJbIKN6LiMGko6/t0St8/7CAte 2aEaN7Myt9ltzQaRZ12PVawVk66JYk+y4blq8nbvoR5TV63lajW32Zy+DO6wNlIEDvVy j+FO11rlEBDxfLjLACCgYnnw65DVgMrJNTlsxCW/kRi3s3SrIBe7NK63pKxZ/94rxsKI F6zA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id z3si482458iof.273.2018.02.08.11.28.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Feb 2018 11:28:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrqA-00081O-69; Thu, 08 Feb 2018 19:26:38 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ejrq9-000814-7U for xen-devel@lists.xen.org; Thu, 08 Feb 2018 19:26:37 +0000 X-Inumbo-ID: 85eecef4-0d05-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 85eecef4-0d05-11e8-b9b1-635ca7ef6cff; Thu, 08 Feb 2018 19:23:20 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 064A61435; Thu, 8 Feb 2018 11:22:25 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EB8203F24D; Thu, 8 Feb 2018 11:22:23 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Thu, 8 Feb 2018 19:21:58 +0000 Message-Id: <20180208192203.9556-11-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180208192203.9556-1-julien.grall@arm.com> References: <20180208192203.9556-1-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v2 10/15] xen/arm: smccc: Implement SMCCC v1.1 inline primitive X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" One of the major improvement of SMCCC v1.1 is that it only clobbers the first 4 registers, both on 32 and 64bit. This means that it becomes very easy to provide an inline version of the SMC call primitive, and avoid performing a function call to stash the registers that woudl otherwise be clobbered by SMCCC v1.0. This patch has been adapted to Xen from Linux commit f2d3b2e8759a. The changes mades are: - Using Xen coding style - Remove HVC as not used by Xen - Add arm_smccc_res structure Reviewed-by: Robin Murphy Tested-by: Ard Biesheuvel Signed-off-by: Marc Zyngier Signed-off-by: Catalin Marinas Signed-off-by: Julien Grall --- Note that the patch is in arm64/for-next/core and should be merged in master soon. Changes in v2: - Patch added --- xen/include/asm-arm/smccc.h | 119 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index bc067892c7..154772b728 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -78,6 +78,125 @@ static inline uint32_t smccc_get_owner(register_t funcid) return (funcid >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK; } +/* + * struct arm_smccc_res - Result from SMC call + * @a0 - @a3 result values from registers 0 to 3 + */ +struct arm_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +/* SMCCC v1.1 implementation madness follows */ +#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x + +#define __count_args(...) \ + ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) + +#define __constraint_write_0 \ + "+r" (r0), "=&r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_1 \ + "+r" (r0), "+r" (r1), "=&r" (r2), "=&r" (r3) +#define __constraint_write_2 \ + "+r" (r0), "+r" (r1), "+r" (r2), "=&r" (r3) +#define __constraint_write_3 \ + "+r" (r0), "+r" (r1), "+r" (r2), "+r" (r3) +#define __constraint_write_4 __constraint_write_3 +#define __constraint_write_5 __constraint_write_4 +#define __constraint_write_6 __constraint_write_5 +#define __constraint_write_7 __constraint_write_6 + +#define __constraint_read_0 +#define __constraint_read_1 +#define __constraint_read_2 +#define __constraint_read_3 +#define __constraint_read_4 "r" (r4) +#define __constraint_read_5 __constraint_read_4, "r" (r5) +#define __constraint_read_6 __constraint_read_5, "r" (r6) +#define __constraint_read_7 __constraint_read_6, "r" (r7) + +#define __declare_arg_0(a0, res) \ + struct arm_smccc_res *___res = res; \ + register uin32_t r0 asm("r0") = a0; \ + register unsigned long r1 asm("r1"); \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_1(a0, a1, res) \ + struct arm_smccc_res *___res = res; \ + register uint32_t r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2"); \ + register unsigned long r3 asm("r3") + +#define __declare_arg_2(a0, a1, a2, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") + +#define __declare_arg_3(a0, a1, a2, a3, res) \ + struct arm_smccc_res *___res = res; \ + register u32 r0 asm("r0") = a0; \ + register typeof(a1) r1 asm("r1") = a1; \ + register typeof(a2) r2 asm("r2") = a2; \ + register typeof(a3) r3 asm("r3") = a3 + +#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + __declare_arg_3(a0, a1, a2, a3, res); \ + register typeof(a4) r4 asm("r4") = a4 + +#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + __declare_arg_4(a0, a1, a2, a3, a4, res); \ + register typeof(a5) r5 asm("r5") = a5 + +#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ + register typeof(a6) r6 asm("r6") = a6 + +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ + register typeof(a7) r7 asm("r7") = a7 + +#define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) +#define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) + +#define ___constraints(count) \ + : __constraint_write_ ## count \ + : __constraint_read_ ## count \ + : "memory" +#define __constraints(count) ___constraints(count) + +/* + * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call + * + * This is a variadic macro taking one to eight source arguments, and + * an optional return structure. + * + * @a0-a7: arguments passed in registers 0 to 7 + * @res: result values from registers 0 to 3 + * + * This macro is used to make SMC calls following SMC Calling Convention v1.1. + * The content of the supplied param are copied to registers 0 to 7 prior + * to the SMC instruction. The return values are updated with the content + * from register 0 to 3 on return from the SMC instruction if not NULL. + * + * We have an output list that is not necessarily used, and GCC feels + * entitled to optimise the whole sequence away. "volatile" is what + * makes it stick. + */ +#define arm_smccc_1_1_smc(...) \ + do { \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile("smc #0\n" \ + __constraints(__count_args(__VA_ARGS__))); \ + if ( ___res ) \ + *___res = (typeof(*___res)){r0, r1, r2, r3}; \ + } while ( 0 ) + #endif /*