| Message ID | 20180209143937.28866-13-andre.przywara@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | New VGIC(-v2) implementation | expand |
Hi Andre, On 09/02/18 14:39, Andre Przywara wrote: > So far the number of list registers (LRs) a GIC implements is only > needed in the hardware facing side of the VGIC code (gic-vgic.c). > The new VGIC will need this information in more and multiple places, so > export a function that returns the number. > > Signed-off-by: Andre Przywara <andre.przywara@linaro.org> > --- > xen/arch/arm/gic-vgic.c | 10 +++++----- > xen/arch/arm/gic.c | 5 +++++ > xen/include/asm-arm/gic.h | 1 + > 3 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c > index d273863556..c92626e4ee 100644 > --- a/xen/arch/arm/gic-vgic.c > +++ b/xen/arch/arm/gic-vgic.c > @@ -25,7 +25,7 @@ > #include <asm/gic.h> > #include <asm/vgic.h> > > -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) > +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_get_nr_lrs()) - 1)) > > #undef GIC_DEBUG > > @@ -110,7 +110,7 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, > struct pending_irq *p, > unsigned int lr) > { > - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; > + unsigned int nr_lrs = gic_get_nr_lrs(); > unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); > struct gic_lr lr_val; > > @@ -137,7 +137,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, > unsigned int priority) > { > int i; > - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; > + unsigned int nr_lrs = gic_get_nr_lrs(); > struct pending_irq *p = irq_to_pending(v, virtual_irq); > > ASSERT(spin_is_locked(&v->arch.vgic.lock)); > @@ -251,7 +251,7 @@ void gic_clear_lrs(struct vcpu *v) > { > int i = 0; > unsigned long flags; > - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; > + unsigned int nr_lrs = gic_get_nr_lrs(); > > /* The idle domain has no LRs to be cleared. Since gic_restore_state > * doesn't write any LR registers for the idle domain they could be > @@ -278,7 +278,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) > struct pending_irq *p, *t, *p_r; > struct list_head *inflight_r; > unsigned long flags; > - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; > + unsigned int nr_lrs = gic_get_nr_lrs(); > int lrs = nr_lrs; > > spin_lock_irqsave(&v->arch.vgic.lock, flags); > diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c > index 968e46fabb..89873c1df4 100644 > --- a/xen/arch/arm/gic.c > +++ b/xen/arch/arm/gic.c > @@ -47,6 +47,11 @@ void register_gic_ops(const struct gic_hw_operations *ops) > gic_hw_ops = ops; > } > > +int gic_get_nr_lrs(void) unsigned int here please. Also, given that gic_hw_ops is exported in gic.h, it would make sense to make that helper static inline in gic.h. > +{ > + return gic_hw_ops->info->nr_lrs; > +} > + > static void clear_cpu_lr_mask(void) > { > this_cpu(lr_mask) = 0ULL; > diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h > index 1d382b0ade..c1f027d703 100644 > --- a/xen/include/asm-arm/gic.h > +++ b/xen/include/asm-arm/gic.h > @@ -222,6 +222,7 @@ enum gic_version { > DECLARE_PER_CPU(uint64_t, lr_mask); > > extern enum gic_version gic_hw_version(void); > +extern int gic_get_nr_lrs(void); > > /* Program the IRQ type into the GIC */ > void gic_set_irq_type(struct irq_desc *desc, unsigned int type); > Cheers,
diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index d273863556..c92626e4ee 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -25,7 +25,7 @@ #include <asm/gic.h> #include <asm/vgic.h> -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_get_nr_lrs()) - 1)) #undef GIC_DEBUG @@ -110,7 +110,7 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, unsigned int lr) { - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); struct gic_lr lr_val; @@ -137,7 +137,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, unsigned int priority) { int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); struct pending_irq *p = irq_to_pending(v, virtual_irq); ASSERT(spin_is_locked(&v->arch.vgic.lock)); @@ -251,7 +251,7 @@ void gic_clear_lrs(struct vcpu *v) { int i = 0; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); /* The idle domain has no LRs to be cleared. Since gic_restore_state * doesn't write any LR registers for the idle domain they could be @@ -278,7 +278,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) struct pending_irq *p, *t, *p_r; struct list_head *inflight_r; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); int lrs = nr_lrs; spin_lock_irqsave(&v->arch.vgic.lock, flags); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 968e46fabb..89873c1df4 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -47,6 +47,11 @@ void register_gic_ops(const struct gic_hw_operations *ops) gic_hw_ops = ops; } +int gic_get_nr_lrs(void) +{ + return gic_hw_ops->info->nr_lrs; +} + static void clear_cpu_lr_mask(void) { this_cpu(lr_mask) = 0ULL; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 1d382b0ade..c1f027d703 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -222,6 +222,7 @@ enum gic_version { DECLARE_PER_CPU(uint64_t, lr_mask); extern enum gic_version gic_hw_version(void); +extern int gic_get_nr_lrs(void); /* Program the IRQ type into the GIC */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type);
So far the number of list registers (LRs) a GIC implements is only needed in the hardware facing side of the VGIC code (gic-vgic.c). The new VGIC will need this information in more and multiple places, so export a function that returns the number. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> --- xen/arch/arm/gic-vgic.c | 10 +++++----- xen/arch/arm/gic.c | 5 +++++ xen/include/asm-arm/gic.h | 1 + 3 files changed, 11 insertions(+), 5 deletions(-)