From patchwork Fri Feb 9 14:39:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127826 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679660ljc; Fri, 9 Feb 2018 06:42:02 -0800 (PST) X-Google-Smtp-Source: AH8x227F+rdcBPUve0QuITgA3vLBkk/xHrzrViXGqoPo6LvqHODpMcMcuYB4TEn5Mm005P3Rrz/S X-Received: by 10.36.196.8 with SMTP id v8mr3517094itf.92.1518187322604; Fri, 09 Feb 2018 06:42:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187322; cv=none; d=google.com; s=arc-20160816; b=by7A7hEKEMq5PL1ONCiNn4Cqm6nHrIOdMW/aCHlyQLdC62wlsPXEuBuh230aOqoSis RR+qqpWUx4bgVZ5FrNn5foUY1YHHxeIT4qGayzp3+ULppIBMRU5I7GwwxDYB0ZTwUhhq rp90/ntQq0ArneYUYKEWq6ToXzGHyVxXXnvX3vAkPaGLPF1TdH80Y/OnIX+glaj1wmRX 3kx3jSWIfBujTpuDoElK/CSqRc950brSkTq4GiE+0f2jePIgkd4hpzEEvDt6mgl5KHcb bci8XcU88vNDoimaFje6ZPSD8OAYQz7QSToqZoEvsAnGWA4DOdLjLXIw+S5tvOiO70Ct llow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=xcHqvY9sQ3ShmbHRgbLrOK1rJ9hr4g8SxoOKIFXfgqg=; b=W03/B1djzDjxQIAzqCRywTcWDZrOKiYg9gMXHnbHj5gIGQ0Z6BQ1c1WwbHsR5v37VM 4lwms36eNJ4w0iE+OurSlcio0405RULyEXSnhpe2pbQsR+2QYNyHhxIqak1KZG9qyqbG EjY7CJbGQbnmSmuzsBc4rupHkVzVAaUNjDyzt4NTUwA0WkVamE5LbCx5XruAKovTqh33 7XrpjbKRAFYCMF2cVgS+kCNeMg2HyXpCUw/POjzdqpSyQg3MICG/MfixDhoFtW/1kexY CIUOScjpd+kpyxKsj8qnU7oPjKEWKdFe2Ab8oEpuapbSXTAF01eu2U3cJLXcA3iSI+KD 5xLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=CvsjtKXB; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id o5si1673426ioe.184.2018.02.09.06.42.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=CvsjtKXB; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qL-0008Gk-Ts; Fri, 09 Feb 2018 14:40:01 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qK-0008AV-7Q for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:00 +0000 X-Inumbo-ID: 093e9653-0da7-11e8-ba59-bc764e045a96 Received: from mail-wm0-x244.google.com (unknown [2a00:1450:400c:c09::244]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 093e9653-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:39:30 +0100 (CET) Received: by mail-wm0-x244.google.com with SMTP id f71so15762476wmf.0 for ; Fri, 09 Feb 2018 06:39:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=PHBKJnQs8ClNFOKaEbgApn6xaPyBllHBCYU+WymPriI=; b=CvsjtKXB03e5kJCK6ry/dqzeqgsDDQX1QLK8vURi2li32BoKB3nQde9CmrXOD5GcL2 5hLkZgtfIq0DcUBYR1qk0bLmd1wjehAayL9R3YhlaC7T7e5/lR4smZ5HodLVhjMUn3Td 0wd9Wb+/MirkpKb1Aj95oHljkQkCL1/6iGB4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=PHBKJnQs8ClNFOKaEbgApn6xaPyBllHBCYU+WymPriI=; b=uCaq/x+tpTP9gBJ0EY2pPRfyF0BvvE2XdrVLKExwvpiQtjQxWlAkO/GX76TRon5qEM wyjgqyJ5m3iq6OAF2McfiypGDwFDxsPha6Z2+sYjVmC8Z6a4873K+JkwqpGtL0muOIA7 zYSXIIPckpehJEM/Aj7oPVCZxNlXu/RZTxJzVn3PZTD39lLwjAA5EsjC0a4z2O95wouM tO7cGD/B+OBjKr2jhIPRWd33umKgZd6MFtYE/WPyUZarMW5if+oukn3V+MJmFW4ncOVY X7jXqhCJwxavnH0X3VUjyjrKfL/6yzzPRYL4LYWs8DZZoh4C55PTYT011PO2PP7j1mkY /Z4w== X-Gm-Message-State: APf1xPA3WySgeH+JSbebRykExidYhGzRhvfeNnyZ/5BVWkldKPt235LJ 1mSsPbhU3W6zJYkUGNisD50ZWP7LIn8= X-Received: by 10.28.96.86 with SMTP id u83mr2102930wmb.63.1518187197852; Fri, 09 Feb 2018 06:39:57 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.39.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:39:57 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:00 +0000 Message-Id: <20180209143937.28866-13-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 12/49] ARM: VGIC: introduce gic_get_nr_lrs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" So far the number of list registers (LRs) a GIC implements is only needed in the hardware facing side of the VGIC code (gic-vgic.c). The new VGIC will need this information in more and multiple places, so export a function that returns the number. Signed-off-by: Andre Przywara --- xen/arch/arm/gic-vgic.c | 10 +++++----- xen/arch/arm/gic.c | 5 +++++ xen/include/asm-arm/gic.h | 1 + 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index d273863556..c92626e4ee 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -25,7 +25,7 @@ #include #include -#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_hw_ops->info->nr_lrs) - 1)) +#define lr_all_full() (this_cpu(lr_mask) == ((1 << gic_get_nr_lrs()) - 1)) #undef GIC_DEBUG @@ -110,7 +110,7 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, unsigned int lr) { - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); unsigned long *lr_mask = (unsigned long *) &this_cpu(lr_mask); struct gic_lr lr_val; @@ -137,7 +137,7 @@ void gic_raise_guest_irq(struct vcpu *v, unsigned int virtual_irq, unsigned int priority) { int i; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); struct pending_irq *p = irq_to_pending(v, virtual_irq); ASSERT(spin_is_locked(&v->arch.vgic.lock)); @@ -251,7 +251,7 @@ void gic_clear_lrs(struct vcpu *v) { int i = 0; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); /* The idle domain has no LRs to be cleared. Since gic_restore_state * doesn't write any LR registers for the idle domain they could be @@ -278,7 +278,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) struct pending_irq *p, *t, *p_r; struct list_head *inflight_r; unsigned long flags; - unsigned int nr_lrs = gic_hw_ops->info->nr_lrs; + unsigned int nr_lrs = gic_get_nr_lrs(); int lrs = nr_lrs; spin_lock_irqsave(&v->arch.vgic.lock, flags); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 968e46fabb..89873c1df4 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -47,6 +47,11 @@ void register_gic_ops(const struct gic_hw_operations *ops) gic_hw_ops = ops; } +int gic_get_nr_lrs(void) +{ + return gic_hw_ops->info->nr_lrs; +} + static void clear_cpu_lr_mask(void) { this_cpu(lr_mask) = 0ULL; diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 1d382b0ade..c1f027d703 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -222,6 +222,7 @@ enum gic_version { DECLARE_PER_CPU(uint64_t, lr_mask); extern enum gic_version gic_hw_version(void); +extern int gic_get_nr_lrs(void); /* Program the IRQ type into the GIC */ void gic_set_irq_type(struct irq_desc *desc, unsigned int type);