From patchwork Fri Feb 9 14:39:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 127858 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp679822ljc; Fri, 9 Feb 2018 06:42:10 -0800 (PST) X-Google-Smtp-Source: AH8x225x38MHRv1ljDkFUQnWZEOyYp3mjMHrZXuihUnx7VbvT2a1OFD0eZBPGg00dM8LU+clVH5t X-Received: by 10.36.242.3 with SMTP id j3mr3687273ith.49.1518187330866; Fri, 09 Feb 2018 06:42:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518187330; cv=none; d=google.com; s=arc-20160816; b=RkYl96qqVHeJCVYof9uAm56/tSVlqyBbrkX0F0FIu7Uw4YwCWctLr9UUddxS77tjOE WS/aOKQq1qnr2ztXtKQN8KxoOrVO+F2ekGCAqaPUahIaYQLsGXCcsI9PQlpYj9HxtBdb VV9wLUdz0M7ITOpunMmYmRCGf7Tvrarsl3pZCha2C2tg4dqeEpLSvpr6q17nAGkSJm4j 5uboFsuwUFAa/u81/9IpxIzX6eMF4in1QztcR6T09lvVRSpO2xCB2/Hj4twkqM4m5bPQ 98n2I3uBL4Psi1NUit/mCPD1Q/QfOa+mg4nLwOWLdl5GYtVZYBs3UE24+zAlWMK+y7Ii rJ5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=fR6UUmffpO/cAz8SaLFlGeYhjU2rNSfR/3S+/ttgMBk=; b=lnCE2Kvie954HCmiord5YNftfhIa5BPfA9MI1iLWQ78EApC7tfFa0HKBgXgE0B1RdL 1TA+hjMPmfLjHqawrKw77cwNeJq+Q162UdnH3FAEtbiNgogCUCohYqNWZtstwWBulA+g 8crZDVee2RuVYdLVcy+zYfFq2HfGyQdMG8WnvL3ssdhxltzxXVl4ocD6ALMUoP4ioE3f zRzC8sE1A9Lcm735ZruC7BT++iXZwICp+x42VNNg5pxZxGazT50+TriuWYnFaRv9T2oe hhVNsbfM4gLcGuXFIM+x27meFRfuQxZCSo24KBUohGR4Wdn3jHg71x+r+5r5nErTDzw7 v6bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d+cZ6aW7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id b75si1713448itd.60.2018.02.09.06.42.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Feb 2018 06:42:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d+cZ6aW7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qd-00015u-Uu; Fri, 09 Feb 2018 14:40:19 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1ek9qc-000121-RY for xen-devel@lists.xenproject.org; Fri, 09 Feb 2018 14:40:18 +0000 X-Inumbo-ID: 149b368b-0da7-11e8-ba59-bc764e045a96 Received: from mail-wr0-x241.google.com (unknown [2a00:1450:400c:c0c::241]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 149b368b-0da7-11e8-ba59-bc764e045a96; Fri, 09 Feb 2018 15:39:49 +0100 (CET) Received: by mail-wr0-x241.google.com with SMTP id o76so5348792wrb.7 for ; Fri, 09 Feb 2018 06:40:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=g88UZvbqFYupt2NXHX1P9U5zn8R80FglujmVgERCgV4=; b=d+cZ6aW7Sl1JvEf2G3BIvB+9ykFyiplxEhSJI0KVM5bsLOYGWTT68S6zWb7HCBF5Lz y7D7Cy5nanuu7+jy/Yjl8c/+hxvEf5qrS2+ZCd96WJEOlA9Y2RlkkodIP+2vjiYf2SZr GZ57AxLRTGjE+gLsrsVSOgvxBO+d+Fg+90J48= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=g88UZvbqFYupt2NXHX1P9U5zn8R80FglujmVgERCgV4=; b=pnc13io34PlKpYvSwqgjdCZ4J/GQWtGRMprUyLUhVLGZVpaF1QZkRm1eemxv2UIxVB SUw+sxJEjCqWOsFOnLhOeX9+Xn3aLFoTQ97qImWrCCH02FP9pqmFZjCoxmr5IIN50CDf eoMw82h1o6uxvqjvoHFXQZ1dZDBnxwTtAtw8I2X/Mh3GYwdiY8tbyAQTm3D91PCzDbWu jVXTb7OK6r+Chx41wXq3yZ2rF9IsXM8NpLPZnABzzANKvSNKysMeJOLhNqgFQj6BjtdY XeyTM+KSwM6rZFh9V96SPJs7uYERBF/mH7mROCxiwezSHEHifq+DRcioT5T/aLqLHPp9 FgPg== X-Gm-Message-State: APf1xPDyXd/YGP4Io5P7sshAZQweyGIHf8NWNwCP8zbWJxf4Ip+k8Db9 tY0PzisHFS/+emCFQ5qEQUECPw== X-Received: by 10.223.145.102 with SMTP id j93mr840574wrj.254.1518187216865; Fri, 09 Feb 2018 06:40:16 -0800 (PST) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id b35sm2552229wra.13.2018.02.09.06.40.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Feb 2018 06:40:16 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall , xen-devel@lists.xenproject.org Date: Fri, 9 Feb 2018 14:39:18 +0000 Message-Id: <20180209143937.28866-31-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180209143937.28866-1-andre.przywara@linaro.org> References: <20180209143937.28866-1-andre.przywara@linaro.org> Subject: [Xen-devel] [RFC PATCH 30/49] ARM: new VGIC: Add ENABLE registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" As the enable register handlers are shared between the v2 and v3 emulation, their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. Signed-off-by: Andre Przywara --- xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 114 +++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 ++++ 3 files changed, 127 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 0926b3243e..eca6840ff9 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -74,10 +74,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_rao, vgic_mmio_write_wi, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISENABLER, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + vgic_mmio_read_enable, vgic_mmio_write_senable, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICENABLER, - vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, + vgic_mmio_read_enable, vgic_mmio_write_cenable, NULL, NULL, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, vgic_mmio_read_raz, vgic_mmio_write_wi, NULL, NULL, 1, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 59703a6909..3d9fa02a10 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -39,6 +39,120 @@ void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, /* Ignore */ } +/* + * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value + * of the enabled bit, so there is only one function for both here. + */ +unsigned long vgic_mmio_read_enable(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + u32 value = 0; + int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->enabled ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +static void vgic_handle_hardware_irq(irq_desc_t *desc, int irq_type, + bool enable) +{ + unsigned long flags; + +// irq_set_affinity(desc, cpumask_of(v_target->processor)); + spin_lock_irqsave(&desc->lock, flags); + if ( enable ) + { + gic_set_irq_type(desc, irq_type == VGIC_CONFIG_LEVEL ? + IRQ_TYPE_LEVEL_HIGH : IRQ_TYPE_EDGE_RISING); + desc->handler->enable(desc); + } + else + desc->handler->disable(desc); + spin_unlock_irqrestore(&desc->lock, flags); +} + +void vgic_mmio_write_senable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + irq_desc_t *desc; + int i; + unsigned long flags; + enum vgic_irq_config config; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + irq->enabled = true; + if ( irq->hw ) + { + /* + * The irq cannot be a PPI, we only support delivery + * of SPIs to guests. + */ + ASSERT(irq->hwintid >= 32); + + desc = irq_to_desc(irq->hwintid); + config = irq->config; + } + else + desc = NULL; + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + + vgic_put_irq(vcpu->domain, irq); + + if ( desc ) + vgic_handle_hardware_irq(desc, config, true); + } +} + +void vgic_mmio_write_cenable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq; + unsigned long flags; + irq_desc_t *desc; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->enabled = false; + + if ( irq->hw ) + desc = irq_to_desc(irq->hwintid); + else + desc = NULL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + + if ( desc ) + vgic_handle_hardware_irq(desc, 0, false); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 10ac682296..9f34bd1aec 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -137,6 +137,17 @@ unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_enable(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_senable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_cenable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); /* Find the proper register handler entry given a certain address offset */