From patchwork Fri Feb 9 16:58:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127865 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802134ljc; Fri, 9 Feb 2018 08:58:14 -0800 (PST) X-Google-Smtp-Source: AH8x224F4YPXQcwNJKjydMpYHZFcGXVU5+FugtN5UHHiS3CmD0RSWbNUO0HR3Rwu28X6ghSEOUF/ X-Received: by 10.28.194.137 with SMTP id s131mr2986030wmf.3.1518195493925; Fri, 09 Feb 2018 08:58:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195493; cv=none; d=google.com; s=arc-20160816; b=HrP8N1LqzVjdb/9yvP2JjnaiI0F3TIlGuPl4k4C22fDTdB12U0IvCO4c1Khn5Li3Xd H3GUkmj9ysNYCtB+bfphJbnDM3+OEj7ja1tQNW5B4WcHMCuV5QmUt08DjwhwSG14xgMj WNLeO2Pcpp6deuAltOcBOJ0Fp5BVF5EtcLKarI0jCVgJyQcgKJHpZVx+w6GCIPRZhvd2 zSB246BmJdSjuD+AT+Oy9Zd9XkSws9x8X97d1Q4+1Aw93x9lpY0qrM19nmxVxU9HRcDa tv354r8DQb9WAv/aWsD8t0sntK++9z+JGgdrUQDB70EUmmWYe2U3jHWuSdtCJJboqf+x kWLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=FUh6YGRZJt0fIcLf6srobD9JR+wnm0STumkuBDvc77g=; b=d8brcW9dMEtPk22nomcjBUYp74H2VGufUg70kVfFLmQZhiji10VYDfBmJ+LF8SxXWu XMUJycvQorntjHJJQmxlv3YUvk1uEZUQmrf9dQYDlUOjcIMDvg8lFnkEyAPgpNC0evB2 e6n3253ByzMR8lEvRfnXrGn9s8CwiGsLIgVHvLvhWH5MTp6Y/H6OYyQEvf4qTrroY4Pi sQRXGGdlET9FXGasVVb9Xla5vwT2M8c0yO8GiYEXXG0jm1PBmdm3CkV/sk87U0YWtLC4 SXGZrvH03RkIHqvHJ1FLaq5nu18mZrbaXp1KZquQSxrBkbsEcCL4rl0A3o0pH2353Jy7 tzRA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id v62si1811102wmd.208.2018.02.09.08.58.13 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC05-0002zZ-El; Fri, 09 Feb 2018 16:58:13 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 02/11] hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling Date: Fri, 9 Feb 2018 16:58:01 +0000 Message-Id: <20180209165810.6668-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had misimplemented this as making the bits RAZ/WI from both Secure and NonSecure states. Fix this bug by checking attrs.secure so that Secure code can pend and unpend NMIs. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 63da0fee34..06b9598fbe 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -830,8 +830,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } } /* NMIPENDSET */ - if ((cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) && - s->vectors[ARMV7M_EXCP_NMI].pending) { + if ((attrs.secure || (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) + && s->vectors[ARMV7M_EXCP_NMI].pending) { val |= (1 << 31); } /* ISRPREEMPT: RES0 when halting debug not implemented */ @@ -1193,7 +1193,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, break; } case 0xd04: /* Interrupt Control State (ICSR) */ - if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { + if (attrs.secure || cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { if (value & (1 << 31)) { armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false); } else if (value & (1 << 30) &&