[v2,03/11] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops

Message ID 20180209165810.6668-4-peter.maydell@linaro.org
State Superseded
Headers show
Series
  • v8m: minor missing regs and bugfixes
Related show

Commit Message

Peter Maydell Feb. 9, 2018, 4:58 p.m.
For M profile cores, cache maintenance operations are done by
writing to special registers in the system register space.
For QEMU, cache operations are always NOPs, since we don't
implement the cache. Implementing these explicitly avoids
a spurious LOG_GUEST_ERROR when the guest uses them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 hw/intc/armv7m_nvic.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

-- 
2.16.1

Comments

Richard Henderson Feb. 9, 2018, 8:34 p.m. | #1
On 02/09/2018 08:58 AM, Peter Maydell wrote:
> For M profile cores, cache maintenance operations are done by

> writing to special registers in the system register space.

> For QEMU, cache operations are always NOPs, since we don't

> implement the cache. Implementing these explicitly avoids

> a spurious LOG_GUEST_ERROR when the guest uses them.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  hw/intc/armv7m_nvic.c | 12 ++++++++++++

>  1 file changed, 12 insertions(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~

Patch

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 06b9598fbe..74b25ce92c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1594,6 +1594,18 @@  static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
         }
         break;
     }
+    case 0xf50: /* ICIALLU */
+    case 0xf58: /* ICIMVAU */
+    case 0xf5c: /* DCIMVAC */
+    case 0xf60: /* DCISW */
+    case 0xf64: /* DCCMVAU */
+    case 0xf68: /* DCCMVAC */
+    case 0xf6c: /* DCCSW */
+    case 0xf70: /* DCCIMVAC */
+    case 0xf74: /* DCCISW */
+    case 0xf78: /* BPIALL */
+        /* Cache and branch predictor maintenance: for QEMU these always NOP */
+        break;
     default:
     bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR,