From patchwork Fri Feb 9 16:58:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127866 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802141ljc; Fri, 9 Feb 2018 08:58:14 -0800 (PST) X-Google-Smtp-Source: AH8x225sjEuCMCf5p/Z+P1veVd2T3RXa68jX9XIk33SiUgTNoq8HN+igNu885ZJ9/ZIu1Wd0zBl2 X-Received: by 10.28.10.6 with SMTP id 6mr2535007wmk.1.1518195494576; Fri, 09 Feb 2018 08:58:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195494; cv=none; d=google.com; s=arc-20160816; b=sFa2cEb581T5wf4y2yd37Jenpa+tV3NCftsfSa53+uiWTmh98z0hzaHP0Q9nROo4j8 yArFEhZk421YvMW5PB9n1jFMhfUKEzIx9Vl4BdK0iqWEuESfjrZHnAzsUjcEWypTsrHL UideiR5AMrrKtqsxpeTkSDmuHwfN/QgPJk7AzggURiSYYSHnvncVqJbo5bi9oEJItEBk D2pRV6rgjuvzfIPRSW8YrfKg8mysgp5pmGCOn/nz8F7higPybqjDRbq6ZRx63l3V+Ivc gC5kPehfywLOuXlRW7BNJ94KujKUsvCVnNmhVF+QlSUT7vaUxPr+Aienx/Rmoo3ett6n fowQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=ryLvpalX9lQiwK3dkujoCkEwiM9hw3XksDW0xnO8TUk=; b=gYoA6gscxVhUNQHdLV5PBsmCZ7241oS2MxsrCQ8ihWnYSDgIuwPilDIQZADy3d+tVd 0Umv2aVbahURRGqvybJmzNNPGp6D96vQ7lXrXYyGVRKUDlitDG5bTi/yTu8ww9ri/cF2 UPydONBLHKuGvuSMbon4nKPW4ZSpfHOraRxEBFI32xNsPv2wOr79TpictSgCteui0O3l FDLLY7AwULN8rl9P/rKiI0m26YmogqV+RZYfv9IYNjC3Owpb8CJDscd0bcbHWJD7bkvG oJHMMV0R5QRgQ5WDglJ3HhJsduRtEIvwDyvdrDyV3wHVywIC5NmaLiN7Az0YkxOXOqfl Rcvg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id n10si1676709wma.106.2018.02.09.08.58.14 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC06-0002zo-4w; Fri, 09 Feb 2018 16:58:14 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 03/11] hw/intc/armv7m_nvic: Implement M profile cache maintenance ops Date: Fri, 9 Feb 2018 16:58:02 +0000 Message-Id: <20180209165810.6668-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> For M profile cores, cache maintenance operations are done by writing to special registers in the system register space. For QEMU, cache operations are always NOPs, since we don't implement the cache. Implementing these explicitly avoids a spurious LOG_GUEST_ERROR when the guest uses them. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 06b9598fbe..74b25ce92c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1594,6 +1594,18 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; } + case 0xf50: /* ICIALLU */ + case 0xf58: /* ICIMVAU */ + case 0xf5c: /* DCIMVAC */ + case 0xf60: /* DCISW */ + case 0xf64: /* DCCMVAU */ + case 0xf68: /* DCCMVAC */ + case 0xf6c: /* DCCSW */ + case 0xf70: /* DCCIMVAC */ + case 0xf74: /* DCCISW */ + case 0xf78: /* BPIALL */ + /* Cache and branch predictor maintenance: for QEMU these always NOP */ + break; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR,