From patchwork Fri Feb 9 16:58:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127867 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802155ljc; Fri, 9 Feb 2018 08:58:15 -0800 (PST) X-Google-Smtp-Source: AH8x225uIbn2HTojVrTH7AxTfMMeZdP5JkjdXZZWbmBtufDs8mkcKT6Z5aUU7KYvGP2R/Ql/QkOv X-Received: by 10.223.139.91 with SMTP id v27mr2894366wra.180.1518195495385; Fri, 09 Feb 2018 08:58:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195495; cv=none; d=google.com; s=arc-20160816; b=sqm0ZVQglV59zNXpfLBcKHV72m2+zegs0IUOeuan2r7imoqwPUltZTg9x5r4v4COKL iIoJvhewB+kVhwup24TmpxPodewFv583d/PWfHdEarIAH3mQRd8UytUEJ/q6g+yCSfkW Rg9s0qzbWuNqn/3jG/gzpuh4Uz84YeGWra06fSgH9xPXi/qXklseJ2k5aY0yjCULJaeW qqy2Mm+KfsKloAEd9uBxyWQFLXgbhP1LZSD8g9jNwukejFo25Ahlc7as7YnQT65IoVTH JUEc+NC/mw6MpLy6g4U4szlYAYSYyn3D2PCUqq2H8hJGwlcaIzHq0xgSRbp3EuZpqQYo DmmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Ec7mIdSwcJgfdIlW71xx0VmWQ297zJiYxFWj8SDvo8g=; b=AdbeA2KpmDpdxwCIJ0wMWB/bRXqZxhgoLgIPvPqQsKX4Tg4ZrpgSBKDzWdxjcEMNH0 fy2Pk4TblZy9fRNaOZHLY8XHiZHvyBCZSRr9ltSk3X7tUVqBePtsF/Mkpz8zhzM74R4S NOoRToRc26TPNoLdlBAmwptNdXFSZ+c2OJo75I6IpcuOYBKdQSafXw1Pm7KTGy1JU9ls Iq2lq4wE5geUevHOiTb5fivfBVoVer4NTXFXrG2J8KLMRvyoNMaiqyPz4+jRtAYGDXCG iPN1gext8oqDKE9pWVSHr5/eAhfOahvS6y+LvyKfUr5l7sk3gIfZfM8LGb460zevwJnQ KjHw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l16si2110349wrl.33.2018.02.09.08.58.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC06-000303-RW; Fri, 09 Feb 2018 16:58:14 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 04/11] hw/intc/armv7m_nvic: Implement v8M CPPWR register Date: Fri, 9 Feb 2018 16:58:03 +0000 Message-Id: <20180209165810.6668-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> The Coprocessor Power Control Register (CPPWR) is new in v8M. It allows software to control whether coprocessors are allowed to power down and lose their state. QEMU doesn't have any notion of power control, so we choose the IMPDEF option of making the whole register RAZ/WI (indicating that no coprocessors can ever power down and lose state). Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.16.1 Reviewed-by: Richard Henderson diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 74b25ce92c..eb49fd77c7 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -776,6 +776,14 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) switch (offset) { case 4: /* Interrupt Control Type. */ return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1; + case 0xc: /* CPPWR */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + /* We make the IMPDEF choice that nothing can ever go into a + * non-retentive power state, which allows us to RAZ/WI this. + */ + return 0; case 0x380 ... 0x3bf: /* NVIC_ITNS */ { int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ; @@ -1175,6 +1183,12 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, ARMCPU *cpu = s->cpu; switch (offset) { + case 0xc: /* CPPWR */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + /* Make the IMPDEF choice to RAZ/WI this. */ + break; case 0x380 ... 0x3bf: /* NVIC_ITNS */ { int startvec = 8 * (offset - 0x380) + NVIC_FIRST_IRQ;