[v2,07/11] target/arm: Implement writing to CONTROL_NS for v8M

Message ID 20180209165810.6668-8-peter.maydell@linaro.org
State Superseded
Headers show
Series
  • v8m: minor missing regs and bugfixes
Related show

Commit Message

Peter Maydell Feb. 9, 2018, 4:58 p.m.
In commit 50f11062d4c896 we added support for MSR/MRS access
to the NS banked special registers, but we forgot to implement
the support for writing to CONTROL_NS. Correct the omission.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

-- 
2.16.1

Comments

Richard Henderson Feb. 9, 2018, 9:08 p.m. | #1
On 02/09/2018 08:58 AM, Peter Maydell wrote:
> In commit 50f11062d4c896 we added support for MSR/MRS access

> to the NS banked special registers, but we forgot to implement

> the support for writing to CONTROL_NS. Correct the omission.

> 

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

> ---

>  target/arm/helper.c | 10 ++++++++++

>  1 file changed, 10 insertions(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>



r~

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 180ab75458..7c1dcb0330 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10519,6 +10519,16 @@  void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
             }
             env->v7m.faultmask[M_REG_NS] = val & 1;
             return;
+        case 0x94: /* CONTROL_NS */
+            if (!env->v7m.secure) {
+                return;
+            }
+            write_v7m_control_spsel_for_secstate(env,
+                                                 val & R_V7M_CONTROL_SPSEL_MASK,
+                                                 M_REG_NS);
+            env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK;
+            env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK;
+            return;
         case 0x98: /* SP_NS */
         {
             /* This gives the non-secure SP selected based on whether we're