From patchwork Fri Feb 9 16:58:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 127872 Delivered-To: patches@linaro.org Received: by 10.46.124.24 with SMTP id x24csp802204ljc; Fri, 9 Feb 2018 08:58:19 -0800 (PST) X-Google-Smtp-Source: AH8x226fjKSD3ftNoW5V2znshdV4rbjol37APKwNsss/j+OebBZj3TdTCbpLUjx/6kLLJQ3HrVpc X-Received: by 10.223.197.67 with SMTP id s3mr2877755wrf.239.1518195499294; Fri, 09 Feb 2018 08:58:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518195499; cv=none; d=google.com; s=arc-20160816; b=AKRCqQqlXLWoeKyq4JG4XrHJgZ4FAJiXufhH3iUNBSEr89ndmTTq0fN8roknyx2tih ZmPt5SXALrHGYY/BdQ2h7DnLb9ii0U5D9eUm4j9UXuuqUyHTC/qrc8TRuRTa6kUC8THV JTOkQ4pmGwD+eRtxK2aqipSMR6apO8YvjqhOoI1QjTHkxMjXrHm+xQG/8bYueeBQRSKf YpIjcFIizlWLbtcs1ErMSZ0dX8b+dPxRQiY4G1rHoTAxnySr0p+aHthalpDcZhPuMPsn PoQge4ivmNSNbgic9zEYMicJwmCNIrzrpIgP1iqThATTEHvjlavblLjuORMR8c9ojGw3 CtSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=fW+o3X2yhpfLWKA90r3Rw7yTLrwIWhhLNnYdCwyW9kw=; b=udTQYtgDXmK1au/JcNiScH5V6bhvxCmb/Znu9Az0a0GuALnRfzGmRC5+9tDZKREhej gA9DxKGjPgMhSdDhiROa3SPCQJnPrbZ81bmZ/CALN5+kmUiDOgeGeX+mQmd1AE9gQzYb XIBNnWkF/aZA4f+iASRy24MHizSsupF0AqLiAvDLVNCjkhZt8yrhNXFncSeZ3azljtax 06tb9oxvp1xXdlaaiLNmBwZ6/PSh5ovOu4C9fetP0LlPu6pNhwkaY6KkASbUNll65tO5 g8zi8nFIKStCtE1q6tdQk8FUYTR5ORAV2K7x7vSUfrS2DFwmMisgfpt9kdufPZTpEcou BOgw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id q5si1892259wre.233.2018.02.09.08.58.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Feb 2018 08:58:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1ekC0A-00031D-RR; Fri, 09 Feb 2018 16:58:18 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH v2 08/11] hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions Date: Fri, 9 Feb 2018 16:58:07 +0000 Message-Id: <20180209165810.6668-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180209165810.6668-1-peter.maydell@linaro.org> References: <20180209165810.6668-1-peter.maydell@linaro.org> MIME-Version: 1.0 In many of the NVIC registers relating to interrupts, we have to convert from a byte offset within a register set into the number of the first interrupt which is affected. We were getting this wrong for: * reads of NVIC_ISPR, NVIC_ISER, NVIC_ICPR, NVIC_ICER, NVIC_IABR -- in all these cases we were missing the "* 8" needed to convert from the byte offset to the interrupt number (since all these registers use one bit per interrupt) * writes of NVIC_IPR had the opposite problem of a spurious "* 8" (since these registers use one byte per interrupt) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/armv7m_nvic.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.16.1 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index ea3b7cce14..c51151fa8a 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1724,7 +1724,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, /* fall through */ case 0x180 ... 0x1bf: /* NVIC Clear enable */ val = 0; - startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */ + startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { if (s->vectors[startvec + i].enabled && @@ -1738,7 +1738,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, /* fall through */ case 0x280 ... 0x2bf: /* NVIC Clear pend */ val = 0; - startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */ + startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { if (s->vectors[startvec + i].pending && (attrs.secure || s->itns[startvec + i])) { @@ -1748,7 +1748,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr, break; case 0x300 ... 0x33f: /* NVIC Active */ val = 0; - startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */ + startvec = 8 * (offset - 0x300) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) { if (s->vectors[startvec + i].active && @@ -1863,7 +1863,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr, case 0x300 ... 0x33f: /* NVIC Active */ return MEMTX_OK; /* R/O */ case 0x400 ... 0x5ef: /* NVIC Priority */ - startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ + startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */ for (i = 0; i < size && startvec + i < s->num_irq; i++) { if (attrs.secure || s->itns[startvec + i]) {