From patchwork Tue Feb 13 13:30:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 128235 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp4255750ljc; Tue, 13 Feb 2018 05:30:19 -0800 (PST) X-Google-Smtp-Source: AH8x224KlgXK/D/827AH2B36img3d1UhBqSLO+E9MZTAqX/14YQZY+VZRFp52noLSYKmkMlyh+xj X-Received: by 10.99.101.3 with SMTP id z3mr1028224pgb.450.1518528618859; Tue, 13 Feb 2018 05:30:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518528618; cv=none; d=google.com; s=arc-20160816; b=IBDVBmnoJRaCQKWeAcwYso97VP8aUD8drNyZKVSBydj5QjoTUGX0OOyWJKroqbc8FQ rH9M1XVx9KSHUN9mzy9ftbSJGhMN+mNwZcBAtkfflsl4IwhSwUncojMSFtGvJv+6DvLY 1n9Rc5tClVXB4Ulgo+csU/TUPHilsaShQZ5lCSwvi9EnHM9OFD69bm3W5ldmYKVynwRZ QtTVTDlsxWanbR0xhEYi9eMN/m97lizVCU0Z5//fRdgmQ6NMZI3EhtsnsvY075yXesIH 6B/7Gi+bxFkSdfM1AU6y7ES5h0BB2b2jfm4NLpBjNv6WZPFPiGJDfJ1pnAXjmFYZj/E3 Hliw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=DGxZpUFmiyl83WsTTqXyZtgrOmV+i4A3AAJ26wvvt2E=; b=pcFz/j3+aW4X51zJKGGQNXkw5xsOVkznu5kityuTfwye3MB7Rqu8mCWdLavRNS725q xVMoodtbNC1zkMAN7EOKFGlsK4UinxXcrC0Sb/IYV4p7togxc4NZ3ORXoWdZ0h4gkTO7 rnMQ5chDPBduOv7nuK+8aNNDnOTA+3Pf4aCoqZbPIPCuYd1DCzQSUQE/3utKmkAZqybS 2/a0LskjwBu9vTq5++ouIu4+SM7H0k5qvCJezCnmf83D6rvLYE1421/QMKHq+CrmLEiV c8ecxy3iDNhH3Pvi68GAuv2Oxl6Mnt6h1/CdBsCrEmVpoRLS7mD/JJ2KNvKxAo39ePXQ 8KRQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o21si4356968pfj.203.2018.02.13.05.30.18; Tue, 13 Feb 2018 05:30:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935410AbeBMNaP (ORCPT + 27 others); Tue, 13 Feb 2018 08:30:15 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:57618 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935174AbeBMNaO (ORCPT ); Tue, 13 Feb 2018 08:30:14 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 196261529; Tue, 13 Feb 2018 05:30:14 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DE90B3F487; Tue, 13 Feb 2018 05:30:13 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 882501AE5430; Tue, 13 Feb 2018 13:30:20 +0000 (GMT) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: Will Deacon , Peter Zijlstra , "Paul E. McKenney" Subject: [PATCH] atomic/bitops: Clarify ordering semantics for failed test_and_{}_bit() Date: Tue, 13 Feb 2018 13:30:19 +0000 Message-Id: <1518528619-20049-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A test_and_{}_bit() operation fails if the value of the bit is such that the modification does not take place. For example, if test_and_set_bit() returns 1. In these cases, follow the behaviour of cmpxchg and allow the operation to be unordered. This also applies to test_and_set_bit_lock() if the lock is found to be be taken already. Cc: Peter Zijlstra Cc: "Paul E. McKenney" Signed-off-by: Will Deacon --- Documentation/atomic_bitops.txt | 7 ++++++- include/asm-generic/bitops/lock.h | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) -- 2.1.4 Acked-by: Peter Zijlstra (Intel) diff --git a/Documentation/atomic_bitops.txt b/Documentation/atomic_bitops.txt index 5550bfdcce5f..be70b32c95d9 100644 --- a/Documentation/atomic_bitops.txt +++ b/Documentation/atomic_bitops.txt @@ -58,7 +58,12 @@ Like with atomic_t, the rule of thumb is: - RMW operations that have a return value are fully ordered. -Except for test_and_set_bit_lock() which has ACQUIRE semantics and + - RMW operations that are conditional are unordered on FAILURE, + otherwise the above rules apply. In the case of test_and_{}_bit() operations, + if the bit in memory is unchanged by the operation then it is deemed to have + failed. + +Except for a successful test_and_set_bit_lock() which has ACQUIRE semantics and clear_bit_unlock() which has RELEASE semantics. Since a platform only has a single means of achieving atomic operations diff --git a/include/asm-generic/bitops/lock.h b/include/asm-generic/bitops/lock.h index bc397573c43a..67ab280ad134 100644 --- a/include/asm-generic/bitops/lock.h +++ b/include/asm-generic/bitops/lock.h @@ -7,7 +7,8 @@ * @nr: Bit to set * @addr: Address to count from * - * This operation is atomic and provides acquire barrier semantics. + * This operation is atomic and provides acquire barrier semantics if + * the returned value is 0. * It can be used to implement bit locks. */ #define test_and_set_bit_lock(nr, addr) test_and_set_bit(nr, addr)