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[209.132.180.67]) by mx.google.com with ESMTP id g67si6540022pgc.690.2018.02.13.06.11.41; Tue, 13 Feb 2018 06:11:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xpj7LMib; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965055AbeBMOLi (ORCPT + 27 others); Tue, 13 Feb 2018 09:11:38 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:40049 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964935AbeBMOLh (ORCPT ); Tue, 13 Feb 2018 09:11:37 -0500 Received: by mail-wm0-f67.google.com with SMTP id v123so16272823wmd.5 for ; Tue, 13 Feb 2018 06:11:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=XYwiMsRR6I6LLIf/qsyo7KHQAbn+dDLHG7JFVeyADxQ=; b=Xpj7LMibq5P45yZ9FhTF8hHW7JsNu+FHVIPDDKrrBlSywVjgwZH+aDncL9dilVCxir bwCqxbA6dmX11FsjyRXt173TShzJPzquSj2pK33o0MQiN84ST4HcOQY2kH255a+KzNYN mZmDnjlCw0VKxEs+2wJYb63CeMm02zEX5MaMA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=XYwiMsRR6I6LLIf/qsyo7KHQAbn+dDLHG7JFVeyADxQ=; b=VuxHAIA262tThIkk2yw+cLmzj2Lmb9gOaPyBiJTMOW5FoRhe74snOmVhfKhrGwy7AQ B9V+R5uNVaG4W/kuZ62qr9UhUUaXF2Mg29YYAMoxHmfix+FfSmo+TVRqZ8h8BuyadryS tofBGpDxgf0gwqWXeo4GszPETRK0NYbo1lqTNvhwRYuZfJhQrWrDakrMO/BBPynmNqYy ilCJLn4Yjw8duCMXdx2Tym8OwL6emJXvsYkJiZhBZWjl8/Hf4puZrX+Eaeg0vEpYGpbK ORsjFAQPQDkoGFZ7XLKixZsvywoKI7PF3MjKnHAq6QOZe9rNAsUZW3G4YxLs4+8e4/rs CLoA== X-Gm-Message-State: APf1xPDxmoMMVIXAw3JQTgMXpf4cX+uz49OU6G6exXx+D2c3R2iAz26q ERMeTzUek2sglJqSKq8M7VQIWQ== X-Received: by 10.28.30.66 with SMTP id e63mr1485754wme.69.1518531095983; Tue, 13 Feb 2018 06:11:35 -0800 (PST) Received: from localhost.localdomain ([196.85.252.149]) by smtp.gmail.com with ESMTPSA id l9sm25186821wrl.1.2018.02.13.06.11.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Feb 2018 06:11:35 -0800 (PST) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com Cc: graeme.gregory@linaro.org, jason@lakedaemon.net, linux-kernel@vger.kernel.org, tglx@linutronix.de, Ard Biesheuvel Subject: [RFC PATCH] irqchip/gic-v3-its: apply ACPI device based quirks Date: Tue, 13 Feb 2018 14:11:18 +0000 Message-Id: <20180213141118.3092-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reapply the SynQuacer quirk for ITS frames that are matched by 'SCX0005' based ACPI devices, replacing the dummy fwnode with the one populated by the ACPI device core. This allows the SynQuacer ACPI tables to publish a device node such as Device (ITS0) { Name (_HID, "SCX0005") Name (_ADR, 0x30020000) Name (_DSD, Package () // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package (2) { "socionext,synquacer-pre-its", Package () { 0x58000000, 0x200000 } }, } }) } which will trigger the existing quirk that replaces the doorbell address with the appropriate address in the pre-ITS frame. Signed-off-by: Ard Biesheuvel --- Marc, Lorenzo, I am aware that this patch may be seen as controversial, but I would like to propose it nonetheless. The reason is that this is the only thing standing in the way of full ACPI support in Socionext SynQuacer based platforms. The pre-ITS is a monstrosity, but as it turns out, Socionext had help from ARM designing it, and the reason we need DT/ACPI based quirks in the first place is that the IIDR of this GICv3 implementation is simply the ARM Ltd. one (as they designed the IP) Please take this into consideration when reviewing this patch, Thanks, Ard. drivers/irqchip/irq-gic-v3-its.c | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) -- 2.11.0 diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 06f025fd5726..a63973baf08a 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3517,3 +3517,42 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists, return 0; } + +#if defined(CONFIG_SOCIONEXT_SYNQUACER_PREITS) && defined(CONFIG_ACPI) +static acpi_status __init acpi_its_device_probe (acpi_handle handle, + u32 depth, void *context, + void **ret) +{ + struct acpi_device *adev; + unsigned long long phys_base; + struct its_node *its; + acpi_status status; + int err; + + err = acpi_bus_get_device(handle, &adev); + if (err) + return AE_CTRL_TERMINATE; + + status = acpi_evaluate_integer(handle, "_ADR", NULL, &phys_base); + if (ACPI_FAILURE(status)) + return status; + + list_for_each_entry(its, &its_nodes, entry) + if (its->phys_base == phys_base) { + irq_domain_free_fwnode(its->fwnode_handle); + its->fwnode_handle = &adev->fwnode; + its_enable_quirk_socionext_synquacer(its); + break; + } + + return AE_CTRL_TERMINATE; +} + +static int __init acpi_its_device_probe_init(void) +{ + if (!acpi_disabled) + acpi_get_devices("SCX0005", acpi_its_device_probe, NULL, NULL); + return 0; +} +subsys_initcall_sync(acpi_its_device_probe_init); +#endif