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[198.145.21.10]) by mx.google.com with ESMTPS id n10-v6si36593plk.255.2018.02.15.09.21.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 09:21:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bmELpXGg; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9544F21F0DA69; Thu, 15 Feb 2018 09:15:24 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 67A0721CF1CE6 for ; Thu, 15 Feb 2018 09:15:22 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id v123so2195095wmd.5 for ; Thu, 15 Feb 2018 09:21:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QYmLPZQGxHt2IVC/aznl+oWrvDMsqQhT1JoEhsDhth4=; b=bmELpXGgOPHL5RzydqFrx2dyWQ55HT16XUZ7uxjO9w5b10ppH3n/dFYy7igK+OjC8h VovNtNjyaR13ZyE/yV8BRbTo18ia/BcJ/KZjpqnMVAtl9PgFk7Kh+zB7vjcrXRsl/dvm ihvoA607/5EJ1Kenhqrbl+iX/8REJovnacDBc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QYmLPZQGxHt2IVC/aznl+oWrvDMsqQhT1JoEhsDhth4=; b=QdQJP0ymsDAqkwM5uglopUcGPKjjFD3ruoEw1EUgNw4KtKAZ96ppaw5kko1wJvo762 XWYg+T0anZn+4YbQ5Ym8iqEH3keratVo/6j2EgLqaaKBa4i9w5liYw5Q45WZ3BqQM2tG fsvEyiHDx0Ce2dixJGnkbaxW3Ot+dcOO96DCwJb+dg1GMchNEEKThksUzvzU+spCKSGG ZfnqbkNBCdbOoEQGBo3fvWpLCQWZiYAiol6yveIcdt12bte2dQBR6FK4ORlcFu98dvr3 pTgHVNdDwnby5epknQXvJDr/wmOx4qPynj+86BziBPBALF0RvWxY6rSLzOodoAJwNHID f/bw== X-Gm-Message-State: APf1xPBei8wVvTza4svjjBGTdCtfT839eFtLfZNwv4vFQ1G7ki8paVvm FlCCs1Z0vtOyi1LAP/RBsTaL0MKcdUU= X-Received: by 10.28.157.206 with SMTP id g197mr2514165wme.96.1518715273598; Thu, 15 Feb 2018 09:21:13 -0800 (PST) Received: from localhost.localdomain ([154.145.114.50]) by smtp.gmail.com with ESMTPSA id j125sm14142363wmd.19.2018.02.15.09.21.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 09:21:12 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 15 Feb 2018 17:20:53 +0000 Message-Id: <20180215172054.27452-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215172054.27452-1-ard.biesheuvel@linaro.org> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: joakim.bech@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" 96boards mezzanines are not runtime discoverable, so it is up to the user to tell the firmware what is connected. So add a pulldown entry that allows a selection to be made: note that boards are only expected to have a single LS connector, so a pulldown is appropriate here. If Secure96 has been selected by the user, install the associated GUID as a protocol, which the Secure96Dxe (which installs the DT overlay into the device tree) has a depex on. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 8 ++++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 6 ++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 8 ++++++++ Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 6 +++++- 5 files changed, 29 insertions(+), 1 deletion(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index aab830dc3a5a..d57d1bbb52fa 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -327,5 +327,13 @@ PlatformDxeEntryPoint ( ASSERT_EFI_ERROR (Status); } + if (mHiiSettings->InstalledMezzanineType == MEZZANINE_SECURE96) { + Handle = NULL; + Status = gBS->InstallProtocolInterface (&Handle, + &gSecure96HardwarePresent, + EFI_NATIVE_INTERFACE, NULL); + ASSERT_EFI_ERROR (Status); + } + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 49d9deee57ea..f3f913609452 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -34,6 +34,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Platform/96boards/Secure96/Secure96.dec Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -59,6 +60,7 @@ [Guids] gEfiHiiPlatformSetupFormsetGuid gFdtTableGuid gNetsecNonDiscoverableDeviceGuid + gSecure96HardwarePresent gSynQuacerNonDiscoverableI2cMasterGuid gSynQuacerNonDiscoverableRuntimeI2cMasterGuid gSynQuacerPlatformFormSetGuid diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni index 2eca8bbba8c3..707540542616 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni @@ -33,3 +33,9 @@ #string STR_EMMC_DISABLED #language en-US "Disabled" #string STR_EMMC_ENABLED #language en-US "Enabled" + +#string STR_MEZZANINE_SELECT_PROMPT #language en-US "96boards mezzanine" +#string STR_MEZZANINE_SELECT_HELP #language en-US "The type of mezzanine board plugged into the 96boards LS connector" + +#string STR_MEZZANINE_NONE #language en-US "None/Unknown" +#string STR_MEZZANINE_SECURE96 #language en-US "Secure96" diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr index ea35e902b2d7..6c348aa0a29b 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr @@ -70,6 +70,14 @@ formset option text = STRING_TOKEN(STR_EMMC_ENABLED), value = EMMC_ENABLED, flags = 0; endoneof; + oneof varid = SynQuacerPlatformSettings.InstalledMezzanineType, + prompt = STRING_TOKEN(STR_MEZZANINE_SELECT_PROMPT), + help = STRING_TOKEN(STR_MEZZANINE_SELECT_HELP), + flags = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_MEZZANINE_NONE), value = MEZZANINE_NONE, flags = DEFAULT; + option text = STRING_TOKEN(STR_MEZZANINE_SECURE96), value = MEZZANINE_SECURE96, flags = 0; + endoneof; + subtitle text = STRING_TOKEN(STR_NULL_STRING); endform; diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h index fbbcbd7d3eec..a723f78a738a 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h @@ -22,12 +22,16 @@ #define PCIE_MAX_SPEED_UNLIMITED 0x0 #define PCIE_MAX_SPEED_GEN1 0x1 +#define MEZZANINE_NONE 0x0 +#define MEZZANINE_SECURE96 0x1 + typedef struct { UINT8 EnableEmmc; UINT8 PcieSlot0MaxSpeed; UINT8 PcieSlot1MaxSpeed; UINT8 PcieSlot2MaxSpeed; - UINT8 Reserved[4]; + UINT8 InstalledMezzanineType; + UINT8 Reserved[3]; } SYNQUACER_PLATFORM_VARSTORE_DATA; #endif