[v2,04/67] target/arm: Implement SVE Bitwise Logical - Unpredicated Group

Message ID 20180217182323.25885-5-richard.henderson@linaro.org
State New
Headers show
Series
  • target/arm: Scalable Vector Extension
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Commit Message

Richard Henderson Feb. 17, 2018, 6:22 p.m.
These were the instructions that were stubbed out when
introducing the decode skeleton.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/translate-sve.c | 50 +++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 43 insertions(+), 7 deletions(-)

-- 
2.14.3

Comments

Peter Maydell Feb. 22, 2018, 6:04 p.m. | #1
On 17 February 2018 at 18:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
> These were the instructions that were stubbed out when

> introducing the decode skeleton.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/translate-sve.c | 50 +++++++++++++++++++++++++++++++++++++++-------

>  1 file changed, 43 insertions(+), 7 deletions(-)

>

> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c

> index 2c9e4733cb..50cf2a1fdd 100644

> --- a/target/arm/translate-sve.c

> +++ b/target/arm/translate-sve.c

> @@ -32,6 +32,10 @@

>  #include "trace-tcg.h"

>  #include "translate-a64.h"

>

> +typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);

> +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,

> +                        uint32_t, uint32_t, uint32_t);


I see we already have these in translate-a64.c -- put them in
translate-a64.h ?

Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


thanks
-- PMM
Richard Henderson Feb. 22, 2018, 7:28 p.m. | #2
On 02/22/2018 10:04 AM, Peter Maydell wrote:
> On 17 February 2018 at 18:22, Richard Henderson

> <richard.henderson@linaro.org> wrote:

>> These were the instructions that were stubbed out when

>> introducing the decode skeleton.

>>

>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>> ---

>>  target/arm/translate-sve.c | 50 +++++++++++++++++++++++++++++++++++++++-------

>>  1 file changed, 43 insertions(+), 7 deletions(-)

>>

>> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c

>> index 2c9e4733cb..50cf2a1fdd 100644

>> --- a/target/arm/translate-sve.c

>> +++ b/target/arm/translate-sve.c

>> @@ -32,6 +32,10 @@

>>  #include "trace-tcg.h"

>>  #include "translate-a64.h"

>>

>> +typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);

>> +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,

>> +                        uint32_t, uint32_t, uint32_t);

> 

> I see we already have these in translate-a64.c -- put them in

> translate-a64.h ?


Good plan, thanks.


r~

Patch

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 2c9e4733cb..50cf2a1fdd 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -32,6 +32,10 @@ 
 #include "trace-tcg.h"
 #include "translate-a64.h"
 
+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+                        uint32_t, uint32_t, uint32_t);
+
 /*
  * Include the generated decoder.
  */
@@ -42,22 +46,54 @@ 
  * Implement all of the translator functions referenced by the decoder.
  */
 
-static void trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn)
+/* Invoke a vector expander on two Zregs.  */
+static void do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
+                         int esz, int rd, int rn)
 {
-    unsupported_encoding(s, insn);
+    unsigned vsz = vec_full_reg_size(s);
+    gvec_fn(esz, vec_full_reg_offset(s, rd),
+            vec_full_reg_offset(s, rn), vsz, vsz);
 }
 
-static void trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn)
+/* Invoke a vector expander on three Zregs.  */
+static void do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
+                         int esz, int rd, int rn, int rm)
 {
-    unsupported_encoding(s, insn);
+    unsigned vsz = vec_full_reg_size(s);
+    gvec_fn(esz, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
+            vec_full_reg_offset(s, rm), vsz, vsz);
 }
 
-static void trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn)
+/* Invoke a vector move on two Zregs.  */
+static void do_mov_z(DisasContext *s, int rd, int rn)
 {
-    unsupported_encoding(s, insn);
+    do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
+}
+
+/*
+ *** SVE Logical - Unpredicated Group
+ */
+
+static void trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+    do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
+}
+
+static void trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+    if (a->rn == a->rm) { /* MOV */
+        do_mov_z(s, a->rd, a->rn);
+    } else {
+        do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
+    }
+}
+
+static void trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+    do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
 }
 
 static void trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn)
 {
-    unsupported_encoding(s, insn);
+    do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
 }