[07/11] clk: meson: axg: add hifi clock bindings

Message ID	20180219112146.21746-8-jbrunet@baylibre.com
State	Accepted
Commit	a4fb7df25de26d12feec4e96687121ec28480a71
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Jerome Brunet <jbrunet@baylibre.com> To: Neil Armstrong <narmstrong@baylibre.com>, Kevin Hilman <khilman@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Carlo Caione <carlo@caione.org>, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/11] clk: meson: axg: add hifi clock bindings Date: Mon, 19 Feb 2018 12:21:42 +0100 Message-Id: <20180219112146.21746-8-jbrunet@baylibre.com> In-Reply-To: <20180219112146.21746-1-jbrunet@baylibre.com> References: <20180219112146.21746-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk
Series	clk: meson: second round of updates \| expand [00/11] clk: meson: second round of updates [01/11] clk: meson: add fractional part of meson8b fixed_pll [02/11] clk: meson: poke pll CNTL last [03/11] clk: meson: remove special gp0 lock loop [04/11] clk: meson: improve pll driver results with frac [05/11] clk: meson: add gp0 frac parameter for axg and gxl [06/11] clk: meson: add ROUND_CLOSEST to the pll driver [07/11] clk: meson: axg: add hifi clock bindings [08/11] clk: meson: axg: add hifi pll clock [09/11] clk: meson: add mpll pre-divider [10/11] clk: meson: add fdiv clock gates [11/11] clk: meson: clean-up clk81 clocks

Message ID

20180219112146.21746-8-jbrunet@baylibre.com

State

Accepted

Commit

a4fb7df25de26d12feec4e96687121ec28480a71

Headers

Received-SPF: pass (google.com: best guess record for domain of
	linux-kernel-owner@vger.kernel.org designates 209.132.180.67
	as permitted sender) client-ip=209.132.180.67; 
From: Jerome Brunet <jbrunet@baylibre.com>
To: Neil Armstrong <narmstrong@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>, Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Carlo Caione <carlo@caione.org>,
	linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 07/11] clk: meson: axg: add hifi clock bindings
Date: Mon, 19 Feb 2018 12:21:42 +0100
Message-Id: <20180219112146.21746-8-jbrunet@baylibre.com>
In-Reply-To: <20180219112146.21746-1-jbrunet@baylibre.com>
References: <20180219112146.21746-1-jbrunet@baylibre.com>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Series

clk: meson: second round of updates | expand

Commit Message

Jerome Brunet Feb. 19, 2018, 11:21 a.m. UTC

Add the new HIFI pll to axg clock bindings

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

---
 include/dt-bindings/clock/axg-clkc.h | 1 +
 1 file changed, 1 insertion(+)

-- 
2.14.3

diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 941ac70e7f30..555937a25504 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -67,5 +67,6 @@ 
 #define CLKID_AO_I2C				58
 #define CLKID_SD_EMMC_B_CLK0			59
 #define CLKID_SD_EMMC_C_CLK0			60
+#define CLKID_HIFI_PLL				69
 
 #endif /* __AXG_CLKC_H */

[07/11] clk: meson: axg: add hifi clock bindings

Commit Message

Patch