From patchwork Fri Feb 23 18:57:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 129483 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp984659edc; Fri, 23 Feb 2018 10:59:48 -0800 (PST) X-Google-Smtp-Source: AG47ELsQK0xB4mXdI/OgCDrQzNUDrZSoMOQW8UQltI9Hn6drWRmtcOJLi5cYRBv1ZCVr9Lmo3j3w X-Received: by 10.107.29.3 with SMTP id d3mr2980075iod.45.1519412388793; Fri, 23 Feb 2018 10:59:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519412388; cv=none; d=google.com; s=arc-20160816; b=RWHE0pvqhb+GtI2P7OEYeZMEX/1zD6WVabasnTops1elcBN1Z3FJUNZS6ThWIDkJFh kVt8Bgmi35X2tACQRTn7cXFWWIKHBbG0bwMkWQ76WENSwrJ0ABvNPlWhRoYZRQ+PD3yY L2TTbPd272vsj5qUv69wK3asuUqZfw3Pj1JqX7NDkCqOCKB0hM/Qhn8uooUIdTVUoNe6 t9nU1tnNzGdh7WSdADIvXaxLRkRBEtQDQU7qsY/I3IxwIwodGKo++rl5rMJbGfSHh/st SW8YWTgK1bxF9S0Q9RRgHsk2zO6hDsOZdQGGFnzEI/NeDu4jzURkzeItbem4MjEfgnNT hZOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=qqRDIGu2XcFPITkJ52v6DdMMs8QvNM9kSbPurA5Lo5k=; b=tdfXdDuG7osYUXDlqBOwp8VLjRcDq3XppmBUqV235y3RG1T5p38YwkXOuUTvtTXL2j hpxihbxBnRig8+ZLtfln7LkgCAEWyKRV32Jvd2Pd5YdhENPjF12XjvHf10qLF/l+lZ1+ c0yWfKkKPm6MXToNdCp1Vh+dchCVDAidFIHlphL2tq//OoTgeg6JH0t+V9kZado+wql4 hPvRf0iJ+lGkhl1tikz3Zc6L6HGe4W65FnUI9dVh1dwlLIAmfBjKmFnyBVgFSp4/L8Y5 puBuYL1/cZZX+F+EBlM10w2QSu7U77cQSdDvrMCPpXhPDJAOv0feC5LRmpCobHG5RStF XcPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id a9si615787ioe.183.2018.02.23.10.59.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXT-0002rr-Ms; Fri, 23 Feb 2018 18:57:47 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXT-0002r9-66 for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:47 +0000 X-Inumbo-ID: 511eaa7d-18cb-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 511eaa7d-18cb-11e8-ba59-bc764e045a96; Fri, 23 Feb 2018 19:56:55 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B97C15AD; Fri, 23 Feb 2018 10:57:45 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 48F953F25C; Fri, 23 Feb 2018 10:57:44 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:17 +0000 Message-Id: <20180223185729.8780-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: Volodymyr Babchuk , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com, andre.przywara@linaro.org Subject: [Xen-devel] [PATCH v5 06/18] xen/arm64: Implement a fast path for handling SMCCC_ARCH_WORKAROUND_1 X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The function SMCCC_ARCH_WORKAROUND_1 will be called by the guest for hardening the branch predictor. So we want the handling to be as fast as possible. As the mitigation is applied on every guest exit, we can check for the call before saving all the context and return very early. For now, only provide a fast path for HVC64 call. Because the code rely on 2 registers, x0 and x1 are saved in advance. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini Reviewed-by: Andre Przywara --- guest_sync only handle 64-bit guest, so I have only implemented the 64-bit side for now. We can discuss whether it is useful to implement it for 32-bit guests. We could also consider to implement the fast path for SMC64, althought a guest should always use HVC. I decided to keep the reviewed-by as mostly the documentation was updated to make it clearer. Changes in v4: - Add Stefano's reviewed-by - Use xzr to clobber x1 instead of x0 - Update comments in the code Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/arm64/entry.S | 59 +++++++++++++++++++++++++++++++++++++++-- xen/include/asm-arm/processor.h | 2 ++ 2 files changed, 59 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S index 6d99e46f0f..ffa9a1c492 100644 --- a/xen/arch/arm/arm64/entry.S +++ b/xen/arch/arm/arm64/entry.S @@ -1,6 +1,7 @@ #include #include #include +#include #include /* @@ -90,8 +91,12 @@ lr .req x30 /* link register */ .endm /* * Save state on entry to hypervisor, restore on exit + * + * save_x0_x1: Does the macro needs to save x0/x1? Defaults to 1 + * If 0, we rely on the on x0/x1 to have been saved at the correct + * position on the stack before. */ - .macro entry, hyp, compat + .macro entry, hyp, compat, save_x0_x1=1 sub sp, sp, #(UREGS_SPSR_el1 - UREGS_LR) /* CPSR, PC, SP, LR */ push x28, x29 push x26, x27 @@ -107,7 +112,16 @@ lr .req x30 /* link register */ push x6, x7 push x4, x5 push x2, x3 + /* + * The caller may already have saved x0/x1 on the stack at the + * correct address and corrupt them with another value. Only + * save them if save_x0_x1 == 1. + */ + .if \save_x0_x1 == 1 push x0, x1 + .else + sub sp, sp, #16 + .endif .if \hyp == 1 /* Hypervisor mode */ @@ -200,7 +214,48 @@ hyp_irq: exit hyp=1 guest_sync: - entry hyp=0, compat=0 + /* + * Save x0, x1 in advance + */ + stp x0, x1, [sp, #-(UREGS_kernel_sizeof - UREGS_X0)] + + /* + * x1 is used because x0 may contain the function identifier. + * This avoids to restore x0 from the stack. + */ + mrs x1, esr_el2 + lsr x1, x1, #HSR_EC_SHIFT /* x1 = ESR_EL2.EC */ + cmp x1, #HSR_EC_HVC64 + b.ne 1f /* Not a HVC skip fastpath. */ + + mrs x1, esr_el2 + and x1, x1, #0xffff /* Check the immediate [0:16] */ + cbnz x1, 1f /* should be 0 for HVC #0 */ + + /* + * Fastest path possible for ARM_SMCCC_ARCH_WORKAROUND_1. + * The workaround has already been applied on the exception + * entry from the guest, so let's quickly get back to the guest. + * + * Note that eor is used because the function identifier cannot + * be encoded as an immediate for cmp. + */ + eor w0, w0, #ARM_SMCCC_ARCH_WORKAROUND_1_FID + cbnz w0, 1f + + /* + * Clobber both x0 and x1 to prevent leakage. Note that thanks + * the eor, x0 = 0. + */ + mov x1, xzr + eret + +1: + /* + * x0/x1 may have been scratch by the fast path above, so avoid + * to save them. + */ + entry hyp=0, compat=0, save_x0_x1=0 /* * The vSError will be checked while SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT * is not set. If a vSError took place, the initial exception will be diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index c0f79d0093..222a02dd99 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h @@ -306,6 +306,8 @@ #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */ #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */ +#define HSR_EC_SHIFT 26 + #define HSR_EC_UNKNOWN 0x00 #define HSR_EC_WFI_WFE 0x01 #define HSR_EC_CP15_32 0x03