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[192.237.175.120]) by mx.google.com with ESMTPS id 94si2001835iom.270.2018.02.23.10.59.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Feb 2018 10:59:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXW-0002up-7b; Fri, 23 Feb 2018 18:57:50 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1epIXV-0002qC-2U for xen-devel@lists.xen.org; Fri, 23 Feb 2018 18:57:49 +0000 X-Inumbo-ID: aaec30e1-18cb-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id aaec30e1-18cb-11e8-b9b1-635ca7ef6cff; Fri, 23 Feb 2018 18:59:26 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8C17315BF; Fri, 23 Feb 2018 10:57:42 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 358B03F25C; Fri, 23 Feb 2018 10:57:41 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Fri, 23 Feb 2018 18:57:15 +0000 Message-Id: <20180223185729.8780-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180223185729.8780-1-julien.grall@arm.com> References: <20180223185729.8780-1-julien.grall@arm.com> Cc: sstabellini@kernel.org, Andre Przywara , andre.przywara@linaro.org, Volodymyr Babchuk , Julien Grall , volodymyr_babchuk@epam.com Subject: [Xen-devel] [PATCH v5 04/18] xen/arm: vsmc: Implement SMCCC_ARCH_WORKAROUND_1 BP hardening support X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" SMCCC 1.1 offers firmware-based CPU workarounds. In particular, SMCCC_ARCH_WORKAROUND_1 provides BP hardening for variant 2 of XSA-254 (CVE-2017-5715). If the hypervisor has some mitigation for this issue, report that we deal with it using SMCCC_ARCH_WORKAROUND_1, as we apply the hypervisor workaround on every guest exit. Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Acked-by: Stefano Stabellini Reviewed-by: Andre Przywara --- Changes in v4: - Add Stefano's acked-by - Add Andre's reviewed-by Changes in v3: - Fix minor conflict during rebase Changes in v2: - Add Volodymyr's reviewed-by --- xen/arch/arm/vsmc.c | 22 ++++++++++++++++++++-- xen/include/asm-arm/smccc.h | 6 ++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vsmc.c b/xen/arch/arm/vsmc.c index 7ec492741b..40a80d5760 100644 --- a/xen/arch/arm/vsmc.c +++ b/xen/arch/arm/vsmc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -93,8 +94,25 @@ static bool handle_arch(struct cpu_user_regs *regs) return true; case ARM_SMCCC_ARCH_FEATURES_FID: - /* Nothing supported yet */ - set_user_reg(regs, 0, ARM_SMCCC_NOT_SUPPORTED); + { + uint32_t arch_func_id = get_user_reg(regs, 1); + int ret = ARM_SMCCC_NOT_SUPPORTED; + + switch ( arch_func_id ) + { + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + if ( cpus_have_cap(ARM_HARDEN_BRANCH_PREDICTOR) ) + ret = 0; + break; + } + + set_user_reg(regs, 0, ret); + + return true; + } + + case ARM_SMCCC_ARCH_WORKAROUND_1_FID: + /* No return value */ return true; } diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 629cc5150b..2951caa49d 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -115,6 +115,12 @@ static inline uint32_t smccc_get_owner(register_t funcid) ARM_SMCCC_OWNER_ARCH, \ 0x1) +#define ARM_SMCCC_ARCH_WORKAROUND_1_FID \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_32, \ + ARM_SMCCC_OWNER_ARCH, \ + 0x8000) + /* SMCCC error codes */ #define ARM_SMCCC_ERR_UNKNOWN_FUNCTION (-1) #define ARM_SMCCC_NOT_SUPPORTED (-1)