| Message ID | 20180227143852.11175-3-alex.bennee@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add ARMv8.2 half-precision functions | expand |
On 27 February 2018 at 14:38, Alex Bennée <alex.bennee@linaro.org> wrote: > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 1 + > target/arm/cpu64.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 8c839faa8f..267a9d7e2f 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1408,6 +1408,7 @@ enum arm_features { > ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ > ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ > ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ > + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ > }; > > static inline int arm_feature(CPUARMState *env, int feature) > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 1c330adc28..9743bdc8c3 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -230,6 +230,7 @@ static void aarch64_any_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_V8_SM4); > set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); > set_feature(&cpu->env, ARM_FEATURE_CRC); > + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); > cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ > cpu->dcz_blocksize = 7; /* 512 bytes */ > } I'm just going to split out the second half of this patchset into its own commit, because we shouldn't enable the feature until after we've implemented it. thanks -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8c839faa8f..267a9d7e2f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1408,6 +1408,7 @@ enum arm_features { ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ ARM_FEATURE_V8_SM3, /* implements SM3 part of v8 Crypto Extensions */ ARM_FEATURE_V8_SM4, /* implements SM4 part of v8 Crypto Extensions */ + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1c330adc28..9743bdc8c3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -230,6 +230,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SM4); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }