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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id p9sm4123698pgs.89.2018.02.28.08.48.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 08:48:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 08:48:13 -0800 Message-Id: <20180228164816.24110-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228164816.24110-1-richard.henderson@linaro.org> References: <20180228164816.24110-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [RISU 1/3] Add aa64 sqrdml[as]h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- aarch64.risu | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.14.3 diff --git a/aarch64.risu b/aarch64.risu index 02e9183..c1a29f6 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2932,6 +2932,30 @@ FCVTZUsi A64_V sf:1 0011110 type:2 1 11 001 000000 rn:5 rd:5 \ # UnallocatedEncoding: type >= 2 FCVTZUsi_RES A64_V sf:1 0011110 1 type:1 1 11 001 000000 rn:5 rd:5 +# +# AdvSIMD v8.1 extensions +# + +@v8_1_simd + +# SQRDMLAH (vector, scalar) +SQRDMLAHvs A64_V81 01111110 size:2 0 rm:5 100001 rn:5 rd:5 +# SQRDMLAH (vector, vector) +SQRDMLAHv A64_V81 0 q:1 101110 size:2 0 rm:5 100001 rn:5 rd:5 +# SQRDMLAH (element, scalar) +SQRDMLAHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1101 h:1 0 rn:5 rd:5 +# SQRDMLAH (element, vector) +SQRDMLAHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1101 h:1 0 rn:5 rd:5 + +# SQRDMLSH (vector, scalar) +SQRDMLSHvs A64_V81 01111110 size:2 0 rm:5 100011 rn:5 rd:5 +# SQRDMLSH (vector, vector) +SQRDMLSHv A64_V81 0 q:1 101110 size:2 0 rm:5 100011 rn:5 rd:5 +# SQRDMLSH (element, scalar) +SQRDMLSHse A64_V81 01111111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5 +# SQRDMLSH (element, vector) +SQRDMLSHve A64_V81 0 q:1 101111 size:2 l:1 m:1 rm:4 1111 h:1 0 rn:5 rd:5 + @ # End of: # Data processing - SIMD and floating point