[edk2,v5,1/6] CorebootPayloadPkg/PciHostBridgeLib: Init PCI aperture to 0

Message ID 1519887444-75510-2-git-send-email-heyi.guo@linaro.org
State New
Headers show
Series
  • Add translation support to generic PciHostBridge
Related show

Commit Message

Guo Heyi March 1, 2018, 6:57 a.m.
Use ZeroMem to initialize all fields in temporary
PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but
helpful for future extension: when we add new fields to
PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can
safely be zero, this code will not suffer from an additional change.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Prince Agyeman <prince.agyeman@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
 CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 5 +++++
 1 file changed, 5 insertions(+)

-- 
2.7.4

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Comments

Ard Biesheuvel March 14, 2018, 11:24 a.m. | #1
On 1 March 2018 at 06:57, Heyi Guo <heyi.guo@linaro.org> wrote:
> Use ZeroMem to initialize all fields in temporary

> PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but

> helpful for future extension: when we add new fields to

> PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can

> safely be zero, this code will not suffer from an additional change.

>

> Contributed-under: TianoCore Contribution Agreement 1.1

> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

> Cc: Maurice Ma <maurice.ma@intel.com>

> Cc: Prince Agyeman <prince.agyeman@intel.com>

> Cc: Benjamin You <benjamin.you@intel.com>

> Cc: Ruiyu Ni <ruiyu.ni@intel.com>

> Cc: Laszlo Ersek <lersek@redhat.com>

> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>


Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>


Maurice, Prince, Benjamin: any comments?

> ---

>  CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 5 +++++

>  1 file changed, 5 insertions(+)

>

> diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c

> index 6d94ff72c956..c61609b79cce 100644

> --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c

> +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c

> @@ -319,6 +319,11 @@ ScanForRootBridges (

>

>    *NumberOfRootBridges = 0;

>    RootBridges = NULL;

> +  ZeroMem (&Io, sizeof (Io));

> +  ZeroMem (&Mem, sizeof (Mem));

> +  ZeroMem (&MemAbove4G, sizeof (MemAbove4G));

> +  ZeroMem (&PMem, sizeof (PMem));

> +  ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));

>

>    //

>    // After scanning all the PCI devices on the PCI root bridge's primary bus,

> --

> 2.7.4

>

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Patch

diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 6d94ff72c956..c61609b79cce 100644
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -319,6 +319,11 @@  ScanForRootBridges (
 
   *NumberOfRootBridges = 0;
   RootBridges = NULL;
+  ZeroMem (&Io, sizeof (Io));
+  ZeroMem (&Mem, sizeof (Mem));
+  ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
+  ZeroMem (&PMem, sizeof (PMem));
+  ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
 
   //
   // After scanning all the PCI devices on the PCI root bridge's primary bus,