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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id y6sm6574381wmy.14.2018.03.05.08.04.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 05 Mar 2018 08:04:43 -0800 (PST) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Mon, 5 Mar 2018 16:03:39 +0000 Message-Id: <20180305160415.16760-22-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180305160415.16760-1-andre.przywara@linaro.org> References: <20180305160415.16760-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 21/57] ARM: GICv2: extend LR read/write functions to cover EOI and source X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" So far our LR read/write functions do not handle the EOI bit and the source CPUID bits in an LR, because the current VGIC implementation does not use them. Extend the gic_lr data structure to hold these bits of information as well, packing it on the way to avoid it to grow. Then extract and assemble those bits from/to an LR. This allows the new VGIC to use this information. Signed-off-by: Andre Przywara Nacked-by: Julien Grall --- Changelog RFC ... v1: - new patch xen/arch/arm/gic-v2.c | 7 +++++++ xen/include/asm-arm/gic.h | 8 +++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 031be920cc..c5ec0d4d35 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -470,6 +470,9 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK; lr_reg->grp = (lrv >> GICH_V2_LR_GRP_SHIFT) & GICH_V2_LR_GRP_MASK; + lr_reg->eoi = !!(lrv & GICH_V2_LR_MAINTENANCE_IRQ); + if ( lr_reg->virq < NR_GIC_SGI ) + lr_reg->source = (lrv >> GICH_V2_LR_CPUID_SHIFT) & GICH_V2_LR_CPUID_MASK; } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) @@ -485,6 +488,10 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK) << GICH_V2_LR_HW_SHIFT) | ((uint32_t)(lr_reg->grp & GICH_V2_LR_GRP_MASK) << GICH_V2_LR_GRP_SHIFT) ); + if ( lr_reg->eoi ) + lrv |= GICH_V2_LR_MAINTENANCE_IRQ; + if ( lr_reg->virq < NR_GIC_SGI ) + lrv |= (uint32_t)lr_reg->source << GICH_V2_LR_CPUID_SHIFT; writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 8fab458d7f..89a07ae6b4 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -223,9 +223,11 @@ struct gic_lr { /* Virtual IRQ */ uint32_t virq; uint8_t priority; - uint8_t state; - uint8_t hw_status; - uint8_t grp; + uint8_t source; + uint8_t state:2; + uint8_t hw_status:1; + uint8_t grp:1; + uint8_t eoi:1; }; enum gic_version {