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[209.132.180.67]) by mx.google.com with ESMTP id t9si957784pfh.101.2018.03.09.06.49.41; Fri, 09 Mar 2018 06:49:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ARKWoHnx; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751183AbeCIOtk (ORCPT + 6 others); Fri, 9 Mar 2018 09:49:40 -0500 Received: from mail-pf0-f195.google.com ([209.85.192.195]:39033 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751102AbeCIOtj (ORCPT ); Fri, 9 Mar 2018 09:49:39 -0500 Received: by mail-pf0-f195.google.com with SMTP id u5so1360590pfh.6 for ; Fri, 09 Mar 2018 06:49:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Djs5vTT2tBE4rW82sTuVYKRpWtCPFi8qZw5yAZsEns8=; b=ARKWoHnx1/z1P/bmsxGPU8DM+vVaWEqNd3Pe3PnQydSxEk/X/E4UR56abdhxOTXwYQ jaHLFR4FdrUnQKzsrxeVAhSsIM89qectCxmOrLz3tdXzRS1l1RMGWa/BtBvKd7eVxM4n LuPtW0FCju0jVGMrIWtZokv6O/V3FbFBdFk5g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Djs5vTT2tBE4rW82sTuVYKRpWtCPFi8qZw5yAZsEns8=; b=FgsAO0BwSNTqCgDgOma3cUBeqkupm0NptGRye2CWYETSOgf/iNDLBq7aGHwc2U5S++ UmJoMe9z+U9JmqBBaEgPBPs4a0koLdHo1X0vMSnOvGxjgIgn5OmSfcZbWCvT1fAdlre6 Xh7/NKmJsv09U4OZF6gs+9DKeg9hMLNtufRBJMed2zeeHG/JOhmLxyhJbNFQXKeZIvzP MjvcE8RvnJqnFu/DZtbnNAH5lOgo0iALIVbbXki+hjjuC8TJZpr+eRAH3TZLtPiJesCv 6YTyVcErLMQNW9XNMd7LlLFG4Hv4UC99Wh1TAbnwv9TBnOqoGv2oOaNL27s7mNkcifQ+ vfVw== X-Gm-Message-State: APf1xPAX9+CIJgSDkY7Yk0rX0cne7kV+/8aAmhIWen2UilgFKneeJn5l NiE7YtnW8C8rseUVXwvQvHdU6g== X-Received: by 10.101.98.137 with SMTP id f9mr23959902pgv.6.1520606978389; Fri, 09 Mar 2018 06:49:38 -0800 (PST) Received: from localhost.localdomain ([104.237.91.63]) by smtp.gmail.com with ESMTPSA id o184sm2919071pga.16.2018.03.09.06.49.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Mar 2018 06:49:37 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengcheng Li , Shawn Guo Subject: [PATCH v5 2/2] phy: add inno-usb2-phy driver for hi3798cv200 SoC Date: Fri, 9 Mar 2018 22:47:01 +0800 Message-Id: <1520606821-22582-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520606821-22582-1-git-send-email-shawn.guo@linaro.org> References: <1520606821-22582-1-git-send-email-shawn.guo@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Pengcheng Li It adds inno-usb2-phy driver for hi3798cv200 SoC USB 2.0 support. One inno-usb2-phy device can support up to two PHY ports. While there is device level reference clock and power reset to be controlled, each PHY port has its own utmi reset that needs to assert/de-assert as needed. Hi3798cv200 needs to access PHY port0 register via particular peripheral syscon controller register to control PHY, like turning on PHY clock. Signed-off-by: Pengcheng Li Signed-off-by: Jiancheng Xue Signed-off-by: Shawn Guo --- drivers/phy/hisilicon/Kconfig | 10 ++ drivers/phy/hisilicon/Makefile | 1 + drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 197 +++++++++++++++++++++++++++++ 3 files changed, 208 insertions(+) create mode 100644 drivers/phy/hisilicon/phy-hisi-inno-usb2.c -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig index 6164c4cd0f65..c21470eb7fba 100644 --- a/drivers/phy/hisilicon/Kconfig +++ b/drivers/phy/hisilicon/Kconfig @@ -11,6 +11,16 @@ config PHY_HI6220_USB To compile this driver as a module, choose M here. +config PHY_HISI_INNO_USB2 + tristate "HiSilicon INNO USB2 PHY support" + depends on (ARCH_HISI && ARM64) || COMPILE_TEST + select GENERIC_PHY + select MFD_SYSCON + help + Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports + USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one + USB host port to accept one USB device. + config PHY_HIX5HD2_SATA tristate "HIX5HD2 SATA PHY Driver" depends on ARCH_HIX5HD2 && OF && HAS_IOMEM diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile index 541b348187a8..e6c979458d3b 100644 --- a/drivers/phy/hisilicon/Makefile +++ b/drivers/phy/hisilicon/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_PHY_HI6220_USB) += phy-hi6220-usb.o +obj-$(CONFIG_PHY_HISI_INNO_USB2) += phy-hisi-inno-usb2.o obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c new file mode 100644 index 000000000000..524381249a2b --- /dev/null +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -0,0 +1,197 @@ +/* + * HiSilicon INNO USB2 PHY Driver. + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include + +#define INNO_PHY_PORT_NUM 2 +#define REF_CLK_STABLE_TIME 100 /* unit:us */ +#define UTMI_CLK_STABLE_TIME 200 /* unit:us */ +#define TEST_CLK_STABLE_TIME 2 /* unit:ms */ +#define PHY_CLK_STABLE_TIME 2 /* unit:ms */ +#define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */ +#define POR_RST_COMPLETE_TIME 300 /* unit:us */ +#define PHY_TEST_DATA GENMASK(7, 0) +#define PHY_TEST_ADDR GENMASK(15, 8) +#define PHY_TEST_PORT GENMASK(18, 16) +#define PHY_TEST_WREN BIT(21) +#define PHY_TEST_CLK BIT(22) /* rising edge active */ +#define PHY_TEST_RST BIT(23) /* low active */ +#define PHY_CLK_ENABLE BIT(2) + +struct hisi_inno_phy_port { + struct reset_control *utmi_rst; + struct hisi_inno_phy_priv *priv; +}; + +struct hisi_inno_phy_priv { + void __iomem *mmio; + struct clk *ref_clk; + struct reset_control *por_rst; + struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM]; +}; + +static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv, + u8 port, u32 addr, u32 data) +{ + void __iomem *reg = priv->mmio; + u32 val; + + val = (data & PHY_TEST_DATA) | + ((addr << 8) & PHY_TEST_ADDR) | + ((port << 16) & PHY_TEST_PORT) | + PHY_TEST_WREN | PHY_TEST_RST; + writel(val, reg); + + val |= PHY_TEST_CLK; + writel(val, reg); + + val &= ~PHY_TEST_CLK; + writel(val, reg); +} + +static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) +{ + /* The phy clk is controlled by the port0 register 0x06. */ + hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE); + msleep(PHY_CLK_STABLE_TIME); +} + +static int hisi_inno_phy_init(struct phy *phy) +{ + struct hisi_inno_phy_port *port = phy_get_drvdata(phy); + struct hisi_inno_phy_priv *priv = port->priv; + int ret; + + ret = clk_prepare_enable(priv->ref_clk); + if (ret) + return ret; + udelay(REF_CLK_STABLE_TIME); + + reset_control_deassert(priv->por_rst); + udelay(POR_RST_COMPLETE_TIME); + + /* Set up phy registers */ + hisi_inno_phy_setup(priv); + + reset_control_deassert(port->utmi_rst); + udelay(UTMI_RST_COMPLETE_TIME); + + return 0; +} + +static int hisi_inno_phy_exit(struct phy *phy) +{ + struct hisi_inno_phy_port *port = phy_get_drvdata(phy); + struct hisi_inno_phy_priv *priv = port->priv; + + reset_control_assert(port->utmi_rst); + reset_control_assert(priv->por_rst); + clk_disable_unprepare(priv->ref_clk); + + return 0; +} + +static const struct phy_ops hisi_inno_phy_ops = { + .init = hisi_inno_phy_init, + .exit = hisi_inno_phy_exit, + .owner = THIS_MODULE, +}; + +static int hisi_inno_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct hisi_inno_phy_priv *priv; + struct phy_provider *provider; + struct device_node *child; + struct resource *res; + int i = 0; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->mmio = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->mmio)) { + ret = PTR_ERR(priv->mmio); + return ret; + } + + priv->ref_clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->ref_clk)) + return PTR_ERR(priv->ref_clk); + + priv->por_rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(priv->por_rst)) + return PTR_ERR(priv->por_rst); + + for_each_child_of_node(np, child) { + struct reset_control *rst; + struct phy *phy; + + rst = of_reset_control_get_exclusive(child, NULL); + if (IS_ERR(rst)) + return PTR_ERR(rst); + priv->ports[i].utmi_rst = rst; + priv->ports[i].priv = priv; + + phy = devm_phy_create(dev, child, &hisi_inno_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_bus_width(phy, 8); + phy_set_drvdata(phy, &priv->ports[i]); + i++; + + if (i > INNO_PHY_PORT_NUM) { + dev_warn(dev, "Support %d ports in maximum\n", i); + break; + } + } + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id hisi_inno_phy_of_match[] = { + { .compatible = "hisilicon,inno-usb2-phy", }, + { .compatible = "hisilicon,hi3798cv200-usb2-phy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match); + +static struct platform_driver hisi_inno_phy_driver = { + .probe = hisi_inno_phy_probe, + .driver = { + .name = "hisi-inno-phy", + .of_match_table = hisi_inno_phy_of_match, + } +}; +module_platform_driver(hisi_inno_phy_driver); + +MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver"); +MODULE_LICENSE("GPL v2");