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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id 1sm1721198wmj.35.2018.03.09.07.11.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Mar 2018 07:11:59 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Fri, 9 Mar 2018 15:11:33 +0000 Message-Id: <20180309151133.31371-18-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180309151133.31371-1-andre.przywara@linaro.org> References: <20180309151133.31371-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 17/17] ARM: GICv2: fix GICH_V2_LR definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The bit definition for the CPUID mask in the GICv2 LR register was wrong, fortunately the current implementation does not use that bit. Fix it up (it's starting at bit 10, not bit 9) and clean up some nearby definitions on the way. This will be used by the new VGIC shortly. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/gic-v2.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index fa9afc2be8..f16e17c1a3 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -57,10 +57,11 @@ #define GICH_V2_LR_HW_MASK 0x1 #define GICH_V2_LR_GRP_SHIFT 30 #define GICH_V2_LR_GRP_MASK 0x1 -#define GICH_V2_LR_MAINTENANCE_IRQ (1<<19) -#define GICH_V2_LR_GRP1 (1<<30) -#define GICH_V2_LR_HW (1<<31) -#define GICH_V2_LR_CPUID_SHIFT 9 +#define GICH_V2_LR_MAINTENANCE_IRQ (1U << 19) +#define GICH_V2_LR_GRP1 (1U << 30) +#define GICH_V2_LR_HW (1U << GICH_V2_LR_HW_SHIFT) +#define GICH_V2_LR_CPUID_SHIFT 10 +#define GICH_V2_LR_CPUID_MASK 0x7 #define GICH_V2_VTR_NRLRGS 0x3f #define GICH_V2_VMCR_PRIORITY_MASK 0x1f