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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id 1sm1721198wmj.35.2018.03.09.07.11.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Mar 2018 07:11:58 -0800 (PST) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Fri, 9 Mar 2018 15:11:31 +0000 Message-Id: <20180309151133.31371-16-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180309151133.31371-1-andre.przywara@linaro.org> References: <20180309151133.31371-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org Subject: [Xen-devel] [PATCH 15/17] ARM: GICv2: introduce gicv2_poke_irq() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The GICv2 uses bitmaps spanning several MMIO registers for holding some interrupt state. Similar to GICv3, add a poke helper functions to set a bit for a given irq_desc in one of those bitmaps. At the moment there is only one use in gic-v2.c, but there will be more coming soon. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/gic-v2.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 2b271ba322..fa9afc2be8 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -235,6 +235,11 @@ static unsigned int gicv2_read_irq(void) return (readl_gicc(GICC_IAR) & GICC_IA_IRQ); } +static void gicv2_poke_irq(struct irq_desc *irqd, uint32_t offset) +{ + writel_gicd(1U << (irqd->irq % 32), offset + (irqd->irq / 32) * 4); +} + static void gicv2_set_irq_type(struct irq_desc *desc, unsigned int type) { uint32_t cfg, actual, edgebit; @@ -509,7 +514,6 @@ static unsigned int gicv2_read_apr(int apr_reg) static void gicv2_irq_enable(struct irq_desc *desc) { unsigned long flags; - int irq = desc->irq; ASSERT(spin_is_locked(&desc->lock)); @@ -517,20 +521,19 @@ static void gicv2_irq_enable(struct irq_desc *desc) clear_bit(_IRQ_DISABLED, &desc->status); dsb(sy); /* Enable routing */ - writel_gicd((1u << (irq % 32)), GICD_ISENABLER + (irq / 32) * 4); + gicv2_poke_irq(desc, GICD_ISENABLER); spin_unlock_irqrestore(&gicv2.lock, flags); } static void gicv2_irq_disable(struct irq_desc *desc) { unsigned long flags; - int irq = desc->irq; ASSERT(spin_is_locked(&desc->lock)); spin_lock_irqsave(&gicv2.lock, flags); /* Disable routing */ - writel_gicd(1u << (irq % 32), GICD_ICENABLER + (irq / 32) * 4); + gicv2_poke_irq(desc, GICD_ICENABLER); set_bit(_IRQ_DISABLED, &desc->status); spin_unlock_irqrestore(&gicv2.lock, flags); }