From patchwork Fri Mar 9 16:35:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131159 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1195070lja; Fri, 9 Mar 2018 08:37:52 -0800 (PST) X-Google-Smtp-Source: AG47ELti5iteNWQJPivrzuJs8uh+ONmy8wRwZuukq1jN+ia0Ly6BGXjB7DB+RJvtwrBSpRHc6zLA X-Received: by 10.107.143.23 with SMTP id r23mr36172470iod.191.1520613472303; Fri, 09 Mar 2018 08:37:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613472; cv=none; d=google.com; s=arc-20160816; b=HDE8nrnW9ye5gkDhxCO0jMF5NsijdrMULPaZ9N6pVa5wHeh7XVF8fSCsvtoix1F8Z+ 6MlCgHYLlgQc8ZJc62hjpSga8yGjwU8ZccTLJADLePdpZoI+mxuVAzgzmIpZhIv3eUKd qlb2OnKcU2+ExzA0mvH/S1omXgom/f4xK21sKranJFrTQiAwXh/hvk74f41tO4C4jrlC BB/SPNLXEhL7fMMk/QxFq57K3cz75CdSFYl52MVpk81EhNnjsOjNsrVBI7Ug8FFYhNS9 LU9c6GRFvmpXmmbV17kUNUIIwJjv7B0umfYegmLH6NAsuVQcvAuWzqBn5xiSHnC9B/Dl 5Xrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=VN+NybTp+RfRcGS4iqg3AWvAvaU9yZ6vBHcVGkxWO+Q=; b=dUb+75tpBm4OVi4iplNEaOmLCx5w1hRLJoPqLVg3FQWvN5FTehaTZMP6HYYjmnOOfy 67MZViN0TYrNwyyfGKHbOS0kUggW2csV5hODTmx+Qa/E73QdVc+xa35LLodr7w+n3+bS bHwEmY/a9/3/2ULjPCmAWX1jmO1dZc3jrYfnJySkeYkQQ82VBaA23Z6aYSVdzq+aGWeD PN+2avclyggPSxLEB/PvxDr5xQvQx2tBSsD3TpumaMci7PJB+OiWev6tsQgUFoK4U81z 1o4IzJoOJvzDP8LlO3PHq18FY7Bn+Wl8KEpFxCnzstBDaHd6uK7vgPtJuRt9J3JMW0Pr dxGg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p69si1198318iod.279.2018.03.09.08.37.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:37:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzQ-0000hE-JE; Fri, 09 Mar 2018 16:35:28 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euKzP-0000gU-E5 for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:35:27 +0000 X-Inumbo-ID: b3ae79ca-23b7-11e8-ba59-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id b3ae79ca-23b7-11e8-ba59-bc764e045a96; Fri, 09 Mar 2018 17:34:13 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 54C241529; Fri, 9 Mar 2018 08:35:25 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 45B5F3F487; Fri, 9 Mar 2018 08:35:24 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:11 +0000 Message-Id: <20180309163511.18808-7-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org, Andre Przywara Subject: [Xen-devel] [PATCH 6/6] ARM: GIC: extend LR read/write functions to cover EOI and source X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Andre Przywara So far our LR read/write functions do not handle the EOI bit and the source CPUID bits in an LR, because the current VGIC implementation does not use them. Extend the gic_lr data structure to hold these bits of information by using a union to differentiate field used depending on whether the vIRQ has a corresponding pIRQ. Note that source is not covered by GICv3 LR. This allows the new VGIC to use this information. Signed-off-by: Andre Przywara Signed-off-by: Julien Grall --- xen/arch/arm/gic-v2.c | 22 +++++++++++++++++++--- xen/arch/arm/gic-v3.c | 11 +++++++++-- xen/include/asm-arm/gic.h | 16 ++++++++++++++-- 3 files changed, 42 insertions(+), 7 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index daf8c61258..69f8d6044a 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -474,8 +474,17 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) if ( lr_reg->hw_status ) { - lr_reg->pirq = lrv >> GICH_V2_LR_PHYSICAL_SHIFT; - lr_reg->pirq &= GICH_V2_LR_PHYSICAL_MASK; + lr_reg->h.pirq = lrv >> GICH_V2_LR_PHYSICAL_SHIFT; + lr_reg->h.pirq &= GICH_V2_LR_PHYSICAL_MASK; + } + else + { + lr_reg->v.eoi = (lrv & GICH_V2_LR_MAINTENANCE_IRQ) == GICH_V2_LR_MAINTENANCE_IRQ; + /* + * This is only valid for SGI, but it does not matter to always + * read it as it should be 0 by default. + */ + lr_reg->v.source = (lrv >> GICH_V2_LR_CPUID_SHIFT) & GICH_V2_LR_CPUID_MASK; } } @@ -496,7 +505,14 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) if ( lr_reg->hw_status ) { lrv |= GICH_V2_LR_HW; - lrv |= lr_reg->pirq << GICH_V2_LR_PHYSICAL_SHIFT; + lrv |= lr_reg->h.pirq << GICH_V2_LR_PHYSICAL_SHIFT; + } + else + { + if ( lr_reg->v.eoi ) + lrv |= GICH_V2_LR_MAINTENANCE_IRQ; + if ( lr_reg->virq < NR_GIC_SGI ) + lrv |= (uint32_t)lr_reg->v.source << GICH_V2_LR_CPUID_SHIFT; } writel_gich(lrv, GICH_LR + lr * 4); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index f73d386df1..a855069111 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1014,7 +1014,9 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->hw_status = (lrv & ICH_LR_HW) == ICH_LR_HW; if ( lr_reg->hw_status ) - lr_reg->pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; + lr_reg->h.pirq = (lrv >> ICH_LR_PHYSICAL_SHIFT) & ICH_LR_PHYSICAL_MASK; + else + lr_reg->v.eoi = (lrv & ICH_LR_MAINTENANCE_IRQ) == ICH_LR_MAINTENANCE_IRQ; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) @@ -1033,7 +1035,12 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) if ( lr->hw_status ) { lrv |= ICH_LR_HW; - lrv |= (uint64_t)lr->pirq << ICH_LR_PHYSICAL_SHIFT; + lrv |= (uint64_t)lr->h.pirq << ICH_LR_PHYSICAL_SHIFT; + } + else + { + if ( lr->v.eoi ) + lrv |= ICH_LR_MAINTENANCE_IRQ; } /* diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 545901b120..4cf5bb385d 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -204,14 +204,26 @@ union gic_state_data { * The LR register format is different for GIC HW version */ struct gic_lr { - /* Physical IRQ -> Only set when hw_status is set. */ - uint32_t pirq; /* Virtual IRQ */ uint32_t virq; uint8_t priority; bool active; bool pending; bool hw_status; + union + { + /* Only filled when there are a corresponding pIRQ (hw_state = true) */ + struct + { + uint32_t pirq; + } h; + /* Only filled when there are no corresponding pIRQ (hw_state = false) */ + struct + { + bool eoi; + uint8_t source; /* GICv2 only */ + } v; + }; }; enum gic_version {