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[192.237.175.120]) by mx.google.com with ESMTPS id d26si1142274iob.50.2018.03.09.08.39.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:39:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL1N-0001GW-Ad; Fri, 09 Mar 2018 16:37:29 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL1M-0001Fj-BT for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:37:28 +0000 X-Inumbo-ID: 3514f618-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 3514f618-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:50 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D116E165C; Fri, 9 Mar 2018 08:35:22 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E4F903F487; Fri, 9 Mar 2018 08:35:21 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:09 +0000 Message-Id: <20180309163511.18808-5-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 4/6] xen/arm: gic: Split the field state in gic_lr in 2 fields active and pending X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall Mostly making the code nicer to read. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 15 +++++++++++---- xen/arch/arm/gic-v3.c | 12 +++++++++--- xen/arch/arm/gic-vgic.c | 6 +++--- xen/include/asm-arm/gic.h | 3 ++- xen/include/asm-arm/gic_v3_defs.h | 2 ++ 5 files changed, 27 insertions(+), 11 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 23223575a2..90d8f652d3 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -51,6 +51,8 @@ #define GICH_V2_LR_PHYSICAL_SHIFT 10 #define GICH_V2_LR_STATE_MASK 0x3 #define GICH_V2_LR_STATE_SHIFT 28 +#define GICH_V2_LR_PENDING (1U << 28) +#define GICH_V2_LR_ACTIVE (1U << 29) #define GICH_V2_LR_PRIORITY_SHIFT 23 #define GICH_V2_LR_PRIORITY_MASK 0x1f #define GICH_V2_LR_HW_SHIFT 31 @@ -467,7 +469,8 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->pirq = (lrv >> GICH_V2_LR_PHYSICAL_SHIFT) & GICH_V2_LR_PHYSICAL_MASK; lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; - lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; + lr_reg->pending = (lrv & GICH_V2_LR_PENDING) == GICH_V2_LR_PENDING; + lr_reg->active = (lrv & GICH_V2_LR_ACTIVE) == GICH_V2_LR_ACTIVE; lr_reg->hw_status = (lrv & GICH_V2_LR_HW) == GICH_V2_LR_HW; } @@ -478,9 +481,13 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) lrv = ( ((lr_reg->pirq & GICH_V2_LR_PHYSICAL_MASK) << GICH_V2_LR_PHYSICAL_SHIFT) | ((lr_reg->virq & GICH_V2_LR_VIRTUAL_MASK) << GICH_V2_LR_VIRTUAL_SHIFT) | ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK) - << GICH_V2_LR_PRIORITY_SHIFT) | - ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK) - << GICH_V2_LR_STATE_SHIFT) ); + << GICH_V2_LR_PRIORITY_SHIFT) ); + + if ( lr_reg->active ) + lrv |= GICH_V2_LR_ACTIVE; + + if ( lr_reg->pending ) + lrv |= GICH_V2_LR_PENDING; if ( lr_reg->hw_status ) lrv |= GICH_V2_LR_HW; diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 0711e509a6..4dbbf0afd2 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1010,7 +1010,8 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->virq = (lrv >> ICH_LR_VIRTUAL_SHIFT) & ICH_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; - lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK; + lr_reg->pending = (lrv & ICH_LR_STATE_PENDING) == ICH_LR_STATE_PENDING; + lr_reg->active = (lrv & ICH_LR_STATE_ACTIVE) == ICH_LR_STATE_ACTIVE; lr_reg->hw_status = (lrv & ICH_LR_HW) == ICH_LR_HW; } @@ -1020,8 +1021,13 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)| ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | - ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)| - ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) ); + ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT) ); + + if ( lr->active ) + lrv |= ICH_LR_STATE_ACTIVE; + + if ( lr->pending ) + lrv |= ICH_LR_STATE_PENDING; if ( lr->hw_status ) lrv |= ICH_LR_HW; diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index e3cb47e80e..d831b35525 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -189,7 +189,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) return; } - if ( lr_val.state & GICH_LR_ACTIVE ) + if ( lr_val.active ) { set_bit(GIC_IRQ_GUEST_ACTIVE, &p->status); if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && @@ -197,7 +197,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) { if ( p->desc == NULL ) { - lr_val.state |= GICH_LR_PENDING; + lr_val.pending = true; gic_hw_ops->write_lr(i, &lr_val); } else @@ -205,7 +205,7 @@ static void gic_update_one_lr(struct vcpu *v, int i) irq, v->domain->domain_id, v->vcpu_id, i); } } - else if ( lr_val.state & GICH_LR_PENDING ) + else if ( lr_val.pending ) { int q __attribute__ ((unused)) = test_and_clear_bit(GIC_IRQ_GUEST_QUEUED, &p->status); #ifdef GIC_DEBUG diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index daec51499c..c32861d4fa 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -209,7 +209,8 @@ struct gic_lr { /* Virtual IRQ */ uint32_t virq; uint8_t priority; - uint8_t state; + bool active; + bool pending; bool hw_status; }; diff --git a/xen/include/asm-arm/gic_v3_defs.h b/xen/include/asm-arm/gic_v3_defs.h index ccb72cf0f1..817bb0d5c7 100644 --- a/xen/include/asm-arm/gic_v3_defs.h +++ b/xen/include/asm-arm/gic_v3_defs.h @@ -171,6 +171,8 @@ #define ICH_LR_PHYSICAL_SHIFT 32 #define ICH_LR_STATE_MASK 0x3 #define ICH_LR_STATE_SHIFT 62 +#define ICH_LR_STATE_PENDING (1UL << 62) +#define ICH_LR_STATE_ACTIVE (1UL << 63) #define ICH_LR_PRIORITY_MASK 0xff #define ICH_LR_PRIORITY_SHIFT 48 #define ICH_LR_HW_MASK 0x1