From patchwork Fri Mar 9 16:35:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 131162 Delivered-To: patch@linaro.org Received: by 10.46.66.2 with SMTP id p2csp1198383lja; Fri, 9 Mar 2018 08:41:26 -0800 (PST) X-Google-Smtp-Source: AG47ELvYuQJ7KadEpYrL3hVENb07CyzWhU5n1ttAH360WFhGzXHBEYxhVCgBjjeWNnq7GjSGunOv X-Received: by 10.107.59.130 with SMTP id i124mr36001918ioa.129.1520613686289; Fri, 09 Mar 2018 08:41:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520613686; cv=none; d=google.com; s=arc-20160816; b=V21za7uIo71skj3bUvcqXWjyjz5JyfdwwPEz++pAw9fedjtZp4oalYs37Q+EuaXbCN JkiTKr0+2MGEsiAdg3ktlWqU+MzbtP8QzYHfRAGkeLBQH2Ah5GGruBda2Rqm0RXsBo6n wbMqcafOdBVWkSxGRxM2Q9RpgzR+jVdpZ4xS+VeMIz1qwqD6O8UwDdJA+y9Vi8lyLDPM TIxrDsRT1ZBlt3zoQtiGpndiJR0dEXu8850pHpWN7Ut+XqrnFFgvLTMatErxZu1S6GIH I/5h7PzC6Ru0VkKCXuKeq9F43SDDCm4lZ4cheRqRghLlNDsDESf0dHfknHewQqlaKjGn GsrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:cc:references:in-reply-to:message-id:date:to :from:arc-authentication-results; bh=A0QjkeA5prjZKP/qAXO+JMD68p8m7ApX/aYkq0Grw5Q=; b=HaluV+W6l4ujDefdbBR1aX3EPWjbfdB76Eh7zO/5LEZlBKU8bSrFQda+kIbZC8pDxy qYQRuiSsJi8WyXAi3SCIePpywsKttUelF4QNFFZifmm/klnbDEzQyvyRhmelSH2xz9km CcqAeWeTepPPXxWPoY3yADsXECNlkVrtzZidtborW9DC/OSowcbtMw2Ugw3JQxgyYYTk q26DNEkgroxdxBaepA/qhwNxj+OULiWiRTIwhr4PD6iXZEnTrdwqyQun138GBlDGQmjl epf/MyIgDm1EOYKYXvjTvkwC4jhw42IB9Jj3Nuc6KdlnGV2VoGbyHwqbM40H2n24ASeR oP3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p8si1363498ioo.305.2018.03.09.08.41.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Mar 2018 08:41:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL3K-0001aA-0b; Fri, 09 Mar 2018 16:39:30 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1euL3J-0001YA-GZ for xen-devel@lists.xenproject.org; Fri, 09 Mar 2018 16:39:29 +0000 X-Inumbo-ID: 34618d0e-23b8-11e8-b9b1-635ca7ef6cff Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id 34618d0e-23b8-11e8-b9b1-635ca7ef6cff; Fri, 09 Mar 2018 16:37:49 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A636015B2; Fri, 9 Mar 2018 08:35:21 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.206.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BAF613F487; Fri, 9 Mar 2018 08:35:20 -0800 (PST) From: julien.grall@arm.com To: xen-devel@lists.xenproject.org Date: Fri, 9 Mar 2018 16:35:08 +0000 Message-Id: <20180309163511.18808-4-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180309163511.18808-1-julien.grall@arm.com> References: <20180309163511.18808-1-julien.grall@arm.com> Cc: andre.przywara@arm.com, Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 3/6] xen/arm: gic: Use bool instead of uint8_t for the hw_status in gic_lr X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall hw_status can only be 1 or 0. So convert to a bool. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 9 +++++---- xen/arch/arm/gic-v3.c | 8 +++++--- xen/include/asm-arm/gic.h | 2 +- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index fc105c08b8..23223575a2 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -468,7 +468,7 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; - lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK; + lr_reg->hw_status = (lrv & GICH_V2_LR_HW) == GICH_V2_LR_HW; } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) @@ -480,9 +480,10 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK) << GICH_V2_LR_PRIORITY_SHIFT) | ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK) - << GICH_V2_LR_STATE_SHIFT) | - ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK) - << GICH_V2_LR_HW_SHIFT)); + << GICH_V2_LR_STATE_SHIFT) ); + + if ( lr_reg->hw_status ) + lrv |= GICH_V2_LR_HW; writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 0dfa1a1e08..0711e509a6 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1011,7 +1011,7 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK; - lr_reg->hw_status = (lrv >> ICH_LR_HW_SHIFT) & ICH_LR_HW_MASK; + lr_reg->hw_status = (lrv & ICH_LR_HW) == ICH_LR_HW; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) @@ -1021,8 +1021,10 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)| ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)| - ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) | - ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) ); + ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) ); + + if ( lr->hw_status ) + lrv |= ICH_LR_HW; /* * When the guest is using vGICv3, all the IRQs are Group 1. Group 0 diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 1eb08b856e..daec51499c 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -210,7 +210,7 @@ struct gic_lr { uint32_t virq; uint8_t priority; uint8_t state; - uint8_t hw_status; + bool hw_status; }; enum gic_version {