From patchwork Fri Mar 9 17:26:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131176 Delivered-To: patch@linaro.org Received: by 10.80.194.209 with SMTP id u17csp1284320edf; Fri, 9 Mar 2018 09:31:43 -0800 (PST) X-Google-Smtp-Source: AG47ELv+wJKURJT+E/T0j6XFaPfOt0/Su9jwd/XcNK2HjCSXNEZhGOm8K++ZeT6JxBfxFnSOF2B2 X-Received: by 2002:a25:8b92:: with SMTP id j18-v6mr19470778ybl.400.1520616703608; Fri, 09 Mar 2018 09:31:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1520616703; cv=none; d=google.com; s=arc-20160816; b=vERh4C8GY1duh8xfmbaWAgT5AF9xFOPL03l7bGSF+Xy1Wc9dLfi/vKuOVPjjEJ2nYW Qo8WtmPXNcOUYofENo2etxFlwID6vBP+Fmbh7KeYvlK1+EXsnUQ5MmlkeWVD4nhicJA0 272BP2Wo9HdorJVAMCyn4m1pzdpPSj4jSOZJSZLzyNnyxDmGGe7Idga59xruTwFTwxOu 1+RVdAkQOelkQaV+rwt9NMzTcSSnRqqbgNsJGN1eW91wzeW1lmPfzVAwt2FMTqBWXw6L mV1rVaUzvkk5lt/G9VT8R1aw14qTA7Lm67VkPXdynwVbwVswO+mFfOhOrhhiza9ub7UF 3QAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:arc-authentication-results; bh=hCOKUMjCogP4ieR8FDqZLL+sBanSeIuLCF73FfOxYcM=; b=O4QjOwO9oG9Z1wCkHAPZP9fwDaASGa+YcA08A/b+YPaoZekrZLeoCv+rAT3wsuwBuv j6BWf7rq97pNxyPAiGbt6CypdUfMw5lKRZljgZk77FHeW3HOWv2wh++qSKQEOP6tFlox E8aZlLCmx0QbvKtY8ZBzUL/J+4LXibsPzyLSLC19mwcHcJUR+We6dzRqBC1vTYwRopHI KbWGEvfZFFTqK5EJUOxyEiPEQyEeTHfjgjQpzciGA+FqEFojToNxOFw/wyew6tqmYIGq yzArNDOQ+7o+XR7g1bzQuNVaLUiyGWIzeJiIkpZ2kgTZYDqnCZhWWF/LOHMRUC8+kZTF RrLA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p126si245012ywh.787.2018.03.09.09.31.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 09 Mar 2018 09:31:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46820 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1euLrq-0004EB-Ou for patch@linaro.org; Fri, 09 Mar 2018 12:31:42 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59677) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1euLmw-0008Sj-Bl for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1euLmu-00067n-94 for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:38 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:46998) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1euLmt-00063U-T3 for qemu-devel@nongnu.org; Fri, 09 Mar 2018 12:26:36 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1euLms-00077e-Pc for qemu-devel@nongnu.org; Fri, 09 Mar 2018 17:26:34 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 9 Mar 2018 17:26:14 +0000 Message-Id: <20180309172622.4277-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180309172622.4277-1-peter.maydell@linaro.org> References: <20180309172622.4277-1-peter.maydell@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/25] target/arm: Make 'any' CPU just an alias for 'max' X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now we have a working '-cpu max', the linux-user-only 'any' CPU is pretty much the same thing, so implement it that way. For the moment we don't add any of the extra feature bits to the system-emulation "max", because we don't set the ID register bits we would need to to advertise those features as present. Signed-off-by: Peter Maydell Message-id: 20180308130626.12393-5-peter.maydell@linaro.org Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 52 +++++++++++++++++++++++++---------------------- target/arm/cpu64.c | 59 ++++++++++++++++++++++++++---------------------------- 2 files changed, 56 insertions(+), 55 deletions(-) -- 2.16.2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2292ad91f6..022d8c5787 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -970,9 +970,19 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model) ObjectClass *oc; char *typename; char **cpuname; + const char *cpunamestr; cpuname = g_strsplit(cpu_model, ",", 1); - typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname[0]); + cpunamestr = cpuname[0]; +#ifdef CONFIG_USER_ONLY + /* For backwards compatibility usermode emulation allows "-cpu any", + * which has the same semantics as "-cpu max". + */ + if (!strcmp(cpunamestr, "any")) { + cpunamestr = "max"; + } +#endif + typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr); oc = object_class_by_name(typename); g_strfreev(cpuname); g_free(typename); @@ -1716,29 +1726,23 @@ static void arm_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { cortex_a15_initfn(obj); - /* In future we might add feature bits here even if the - * real-world A15 doesn't implement them. - */ - } -} -#endif - #ifdef CONFIG_USER_ONLY -static void arm_any_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); - cpu->midr = 0xffffffff; + /* We don't set these in system emulation mode for the moment, + * since we don't correctly set the ID registers to advertise them, + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); +#endif + } } #endif @@ -1794,7 +1798,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "max", .initfn = arm_max_initfn }, #endif #ifdef CONFIG_USER_ONLY - { .name = "any", .initfn = arm_any_initfn }, + { .name = "any", .initfn = arm_max_initfn }, #endif #endif { .name = NULL } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 89b2f4eaed..991d764674 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -228,38 +228,38 @@ static void aarch64_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { aarch64_a57_initfn(obj); - /* In future we might add feature bits here even if the - * real-world A57 doesn't implement them. +#ifdef CONFIG_USER_ONLY + /* We don't set these in system emulation mode for the moment, + * since we don't correctly set the ID registers to advertise them, + * and in some cases they're only available in AArch64 and not AArch32, + * whereas the architecture requires them to be present in both if + * present in either. */ + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); + set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); + set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + set_feature(&cpu->env, ARM_FEATURE_V8_FP16); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + /* For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. + */ + cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ + cpu->dcz_blocksize = 7; /* 512 bytes */ +#endif } } -#ifdef CONFIG_USER_ONLY -static void aarch64_any_initfn(Object *obj) -{ - ARMCPU *cpu = ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_AARCH64); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM4); - set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); - cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ - cpu->dcz_blocksize = 7; /* 512 bytes */ -} -#endif - typedef struct ARMCPUInfo { const char *name; void (*initfn)(Object *obj); @@ -270,9 +270,6 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, -#ifdef CONFIG_USER_ONLY - { .name = "any", .initfn = aarch64_any_initfn }, -#endif { .name = NULL } };