From patchwork Tue Mar 13 15:34:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131475 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884718ljb; Tue, 13 Mar 2018 08:35:03 -0700 (PDT) X-Google-Smtp-Source: AG47ELua2kDmYToYuUq0mLWPt++6uJkdD/qC7BSbIXPVxKggfvjSjJnBb3nZT17eJ+MU3OoS0/rT X-Received: by 10.223.160.42 with SMTP id k39mr1016647wrk.138.1520955303707; Tue, 13 Mar 2018 08:35:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955303; cv=none; d=google.com; s=arc-20160816; b=mFXrIKN7Omv6cRPp8GvYWVtfTjnuiLOHaW+6J3JMdFUtBrnklrkuPw8dde/Os1ZpFx p38IHNkkZuG45nVP4pzrMqumOZmZbWiggUVQCzo6au2r1HHRcUdWP5OsK7l2z60pMXFv 31CoTrpM1X9ri4ucvGQLrOSIlYvuVpv7ODbgDA0oulpuBQHhxT+bLA9egIL9S3D68hud z6A5ptpKdtfpG/GVG2ICqZSjF0kNGfIP8d8sb2x5r2o6bQrkj776a9JEBIs+OasKjV+W 16bwssXhNV4jd4Q20IVKLorv1yBHh/HxMaucmV3UE0ZmsmKzdLMl3TcGZh7Z9JLjdjki 6l9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=YN47X/zRb0s5EGxfv46/agloo6jzVtVgYZ3CoCh/dvE=; b=NQSdWsoJ9RTGD+NMZFzaokc90wtmolF3jLybpMF7SuKHlWXyUheeuWd0ZssnwHSPPM 1CV+bbijNHjFuL+tu8ztaJe1J+QwpueDvyEhlO+dAeTtpcFzKDqwQEBDOpguZfY/2+os t/0sz+EW2Rd0wAiM8U9klAr6L0mwv8Lapnk4Y8LVXk78/XwiQPF+Q7A/ITJv+lfPIZps k71tV7Mf6MmBSbLnOCfd/sQqIrS24mOu8usTX8DOxcj8/RzIMMzvByu4jw528igh/sNY /tYnvJJBWyWXIATbkf+IecyOS8uZNtgmiJq2BCuqV3aJXdnYO0sumjqev9KVXhJyOFQp y15Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id r16si326051wrb.109.2018.03.13.08.35.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx9-0003Em-46; Tue, 13 Mar 2018 15:35:03 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 3/9] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE Date: Tue, 13 Mar 2018 15:34:52 +0000 Message-Id: <20180313153458.26822-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> If we're directly booting a Linux kernel and the CPU supports both EL3 and EL2, we start the kernel in EL2, as it expects. We must also set the SCR_EL3.HCE bit in this situation, so that the HVC instruction is enabled rather than UNDEFing. Otherwise at least some kernels will panic when trying to initialize KVM in the guest. Signed-off-by: Peter Maydell --- hw/arm/boot.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.16.2 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e21a92f972..9319b12fcd 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -729,6 +729,11 @@ static void do_cpu_reset(void *opaque) assert(!info->secure_board_setup); } + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* If we have EL2 then Linux expects the HVC insn to work */ + env->cp15.scr_el3 |= SCR_HCE; + } + /* Set to non-secure if not a secure boot */ if (!info->secure_boot && (cs != first_cpu || !info->secure_board_setup)) {