From patchwork Tue Mar 13 15:34:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131481 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884796ljb; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) X-Google-Smtp-Source: AG47ELvxH2raNeu5JbMT4l0MDEB4EKf0VSFdqH4l9ubJXdxUuVUkIyHGRgOlKtndk9Xju1UaQKgF X-Received: by 10.223.158.196 with SMTP id b4mr1006392wrf.112.1520955307195; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955307; cv=none; d=google.com; s=arc-20160816; b=Ze6BVnSd3BDwlpZTylXGIM/UFJQ5/ZLHtIuJJpojsNmGzJ1Z1c5TA/uQaSyZEkpdL+ ewDI4y8Y1oxIE/HKctVANii1TVUczt3sq/4p0HdOvDYl05nomq5YC4dDEK0NIiNUkmzp MGz9n11T0neY4hlLQGZXT3AB35e3TiY/4oSxWKfFaEAIN9+Ic7FSe3YhPC+N5e8UQhvc kDhfyxvVajWKbYtfFOfXthkBhkMGFM7mtMxhBBYklKNHO5eVUlYOnTiBFS3UBkuXtqm/ hNZfRQYWmi8pS2LVrLvGf5uAaCXduTA5xlI9+AAjIVK56ho2mc7XdNz8bztDc2kUjZYN Ow4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=2e9tgmjPvIR2v7LocAzMQtkqqdh+4SwQiNDQfF5WJJc=; b=lku3eWcuxi6bnFoBFUdvtmTIA27KOlQTsmYGs2jTDgquYQVg8Bmgkc3rSQvEw6oLxt we+ruERlFNba0ules7rMSUvKp902YobDOPLAezpjU/tcA3HFVSiebOhwvHNb7dYSibg7 GpXPK+q8ARwT+vbByvb607k05/ZEtt8RoXkjJC9itLaWb8HRY+tjggiRE2La1eRClywR Y77E3i/MuW481mJpmyOgh5sr+M2pfTbQr6J3YMgjW13elKrLpfu9j6W2Ffwg8dZpDPpD Jo341dyKu96np8lmDOHdKP0aT7eAHB4oX5GYkd8Hazt6MQwYbBb+bpo/CWiTZb158yqD eKvw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id p26si313338wrp.224.2018.03.13.08.35.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxC-0003GI-Ne; Tue, 13 Mar 2018 15:35:06 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 8/9] hw/arm/bcm2836: Hardcode correct CPU type Date: Tue, 13 Mar 2018 15:34:57 +0000 Message-Id: <20180313153458.26822-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> Now we have separate types for BCM2386 and BCM2387, we might as well just hard-code the CPU type they use rather than having it passed through as an object property. This then lets us put the initialization of the CPU object in init rather than realize. Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 22 +++++++++++++--------- hw/arm/raspi.c | 2 -- 2 files changed, 13 insertions(+), 11 deletions(-) -- 2.16.2 Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 7140257c98..12f75b55a7 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,16 +25,19 @@ struct BCM283XInfo { const char *name; + const char *cpu_type; int clusterid; }; static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"), .clusterid = 0xf, }, { .name = TYPE_BCM2837, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), .clusterid = 0x0, }, }; @@ -42,6 +45,16 @@ static const BCM283XInfo bcm283x_socs[] = { static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); + BCM283XClass *bc = BCM283X_GET_CLASS(obj); + const BCM283XInfo *info = bc->info; + int n; + + for (n = 0; n < BCM283X_NCPUS; n++) { + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), + info->cpu_type); + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), + &error_abort); + } object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -69,14 +82,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* common peripherals from bcm2835 */ - obj = OBJECT(dev); - for (n = 0; n < BCM283X_NCPUS; n++) { - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), - s->cpu_type); - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), - &error_abort); - } - obj = object_property_get_link(OBJECT(dev), "ram", &err); if (obj == NULL) { error_setg(errp, "%s: required ram link not found: %s", @@ -168,7 +173,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } static Property bcm2836_props[] = { - DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index f588720138..ae15997669 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -150,8 +150,6 @@ static void raspi_init(MachineState *machine, int version) /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", &error_abort); int board_rev = version == 3 ? 0xa02082 : 0xa21041;