From patchwork Tue Mar 13 15:34:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131482 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884808ljb; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) X-Google-Smtp-Source: AG47ELuOkMjoVbl45b1Yxl1iROmVzSrim0IvRZ7CGSfbDLXVL9XpWaqYLn3DCsDz3OgZ+Jav0h8C X-Received: by 2002:a17:902:b407:: with SMTP id x7-v6mr560761plr.373.1520955307477; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955307; cv=none; d=google.com; s=arc-20160816; b=w9g9Ua1IdPBgy8UGOxwt4i7kElmCrbjxNgUbnhE/khjLZub7NoULrPJkfCLFXKP5FI 3jHYJOqdrHETWZgUHpLcC5th0b3vZdaZ58rlaVin4UEcH80MMTLjHHRvP6TRSqA8HMzi 5B/sg9YeAjuM/z6SNMJSztzlEfqYq07KaZQIpHwwX4nwGWAYWYn8qpDVqmA7EnduqJd7 o3YrCNSt4MbGYnhbuRj7Xwhy+p05balLIbf03NqnoR3hX59eYc1LlYSZWg4J3KYsfevU dnM1LJ7nGQ2ROYrqjEbAwqvU6j+nB+SOs4vXPUrBogazwkwbubOxfBKj5Xu/up0aFO5c XUkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Moax0p294uKndt3CiguMn4SsRQy9dHzyxg2cfG3e5vo=; b=0RgHADlj/7BKF6F9tGdqJ+lY7Fp7HKSd2c3YPwF3cVdCMCB+aMZmShC69MvOJrG2l6 ldv84aUPtdmhZ9SZK+A3+5T8nhkx+iz3XJberVqVnb6fPvQXuaW/6AtCuAjocPEVQD55 ZsAY3JAa2onu/vHhXKNz5r75x962EfyzkbuytcCziGDz1eoTUiO0NnA+eSCHjzVTj+NC rQRsYIrh42PNf+psFjulyShEDdtRVlgnxenAJja0YAx2zqRh+KaeGSoXjyS98xDTcqiy glQmjTd/wlmsKP1jEg5NeIKrqZz3dWeB0qmfsG83wqlZKvJyGjchT+Tk/C4pIotFjDmq a3sw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id h10si281408pgc.75.2018.03.13.08.35.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx7-0003EE-O2; Tue, 13 Mar 2018 15:35:01 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 1/9] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 Date: Tue, 13 Mar 2018 15:34:50 +0000 Message-Id: <20180313153458.26822-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> For the rpi1 and 2 we want to boot the Linux kernel via some custom setup code that makes sure that the SMC instruction acts as a no-op, because it's used for cache maintenance. The rpi3 boots AArch64 kernels, which don't need SMC for cache maintenance and always expect to be booted non-secure. Don't fill in the aarch32-specific parts of the binfo struct. Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) -- 2.16.2 Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index a37881433c..1ac0737149 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -82,10 +82,19 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) binfo.board_id = raspi_boardid[version]; binfo.ram_size = ram_size; binfo.nb_cpus = smp_cpus; - binfo.board_setup_addr = BOARDSETUP_ADDR; - binfo.write_board_setup = write_board_setup; - binfo.secure_board_setup = true; - binfo.secure_boot = true; + + if (version <= 2) { + /* The rpi1 and 2 require some custom setup code to run in Secure + * mode before booting a kernel (to set up the SMC vectors so + * that we get a no-op SMC; this is used by Linux to call the + * firmware for some cache maintenance operations. + * The rpi3 doesn't need this. + */ + binfo.board_setup_addr = BOARDSETUP_ADDR; + binfo.write_board_setup = write_board_setup; + binfo.secure_board_setup = true; + binfo.secure_boot = true; + } /* Pi2 and Pi3 requires SMP setup */ if (version >= 2) {