From patchwork Tue Mar 13 15:34:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131483 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884822ljb; Tue, 13 Mar 2018 08:35:08 -0700 (PDT) X-Google-Smtp-Source: AG47ELvghZYahfM3gtiQHT1D9iEXhLTF2WxcxHebPAkvL72hZ1p8d5jbDp+AJub3Wm7EjzzIVSQT X-Received: by 10.223.153.45 with SMTP id x42mr1022437wrb.124.1520955307977; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955307; cv=none; d=google.com; s=arc-20160816; b=Rdn39d4DeXdvW03rTmH0ZLucRKd9uV5VsqpYEKPYouyUw0h0pDl8qanRz526tlMkU5 xeTFJ6Q6jujlcv0y2t2bUjwzihaiF3HrbmXkfUn3k7jeP6mjkRqED/G3AoPoKnrF5sFv EAUAeHEIPStw8qdweWC5GUaip1cRyxdvr3eTE+wx/a9Kq45xyoFDkkZUa1Q7FYYaq7pH wShJd16m9+G7hA7uVYjqO7BdARyEz1z03UZixmVvJPm16yJnXujvhlJR9TgG6KMR4GpB PzZ8uvu+hvGMjsEqQV/n0FlbS/7nJ+81xWStQt7yH7RDCGbm6Z2scv6nmRNuZgrDlcZ5 kRpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=CvnRNeh6ibfMrYNuS93D15H2Eb2EK4mAY4BMUSe1ppY=; b=pgPw9c5hLVd3K6++8rlcybBGbxAkHczCmXaOZ0ZzA4Zyo+HZsEbR/Ul0+Gn3zPStvS W10hk2ulgqG01xKhIr6wEMBm+YkwHUVqwXCkU2YStO0twQe8B+qYtbjK6V1PKRk+Xj9r nQiXtM1IzFWo9zAVnYVs9sUpgL3fLRm7Yq8k7A60bmlcDrRrmYBjgwYBAgHLUfGmBp28 l7x4Tf6I5b7pIc8TF/jlA6Csbvp27J+BpPunCLj6oM9ts/0xaaUAXoEo0HMpsf7O76lk LbeNnYgalI9p/EUw66a49sFm+J3lfQDVoDOSOeGeV3eJW1BkFCF22s0Z4StwamRdvFNA WaMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 198si299650wmo.87.2018.03.13.08.35.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxD-0003Gh-Gd; Tue, 13 Mar 2018 15:35:07 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 9/9] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs Date: Tue, 13 Mar 2018 15:34:58 +0000 Message-Id: <20180313153458.26822-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> The raspi3 has AArch64 CPUs, which means that our smpboot code for keeping the secondary CPUs in a pen needs to have a version for A64 as well as A32. Without this, the secondary CPUs go into an infinite loop of taking undefined instruction exceptions. Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) -- 2.16.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index ae15997669..06f1e08ca9 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -27,6 +27,7 @@ #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ +#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ /* Table of Linux board IDs for different Pi versions */ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; @@ -63,6 +64,40 @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) info->smp_loader_start); } +static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) +{ + /* Unlike the AArch32 version we don't need to call the board setup hook. + * The mechanism for doing the spin-table is also entirely different. + * We must have four 64-bit fields at absolute addresses + * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for + * our CPUs, and which we must ensure are zero initialized before + * the primary CPU goes into the kernel. We put these variables inside + * a rom blob, so that the reset for ROM contents zeroes them for us. + */ + static const uint32_t smpboot[] = { + 0xd2801b05, /* mov x5, 0xd8 */ + 0xd53800a6, /* mrs x6, mpidr_el1 */ + 0x924004c6, /* and x6, x6, #0x3 */ + 0xd503205f, /* spin: wfe */ + 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ + 0xb4ffffc4, /* cbz x4, spin */ + 0xd2800000, /* mov x0, #0x0 */ + 0xd2800001, /* mov x1, #0x0 */ + 0xd2800002, /* mov x2, #0x0 */ + 0xd2800003, /* mov x3, #0x0 */ + 0xd61f0080, /* br x4 */ + }; + + static const uint64_t spintables[] = { + 0, 0, 0, 0 + }; + + rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start); + rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), + SPINTABLE_ADDR); +} + static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); @@ -99,7 +134,11 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) /* Pi2 and Pi3 requires SMP setup */ if (version >= 2) { binfo.smp_loader_start = SMPBOOT_ADDR; - binfo.write_secondary_boot = write_smpboot; + if (version == 2) { + binfo.write_secondary_boot = write_smpboot; + } else { + binfo.write_secondary_boot = write_smpboot64; + } binfo.secondary_cpu_reset_hook = reset_secondary; }