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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id w125sm3217102wmw.20.2018.03.15.13.31.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 Mar 2018 13:31:09 -0700 (PDT) From: Andre Przywara To: Stefano Stabellini , Julien Grall Date: Thu, 15 Mar 2018 20:30:10 +0000 Message-Id: <20180315203050.19791-6-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180315203050.19791-1-andre.przywara@linaro.org> References: <20180315203050.19791-1-andre.przywara@linaro.org> Cc: xen-devel@lists.xenproject.org, Andre Przywara Subject: [Xen-devel] [PATCH v2 05/45] xen/arm: gic: Use bool instead of uint8_t for the hw_status in gic_lr X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall hw_status can only be 1 or 0. So convert to a bool. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara Acked-by: Stefano Stabellini --- Changes: - Remove == *LR_HW as it is pointless - Add Andre's reviewed-by xen/arch/arm/gic-v2.c | 9 +++++---- xen/arch/arm/gic-v3.c | 8 +++++--- xen/include/asm-arm/gic.h | 2 +- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index fc105c08b8..9d589115bd 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -468,7 +468,7 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->virq = (lrv >> GICH_V2_LR_VIRTUAL_SHIFT) & GICH_V2_LR_VIRTUAL_MASK; lr_reg->priority = (lrv >> GICH_V2_LR_PRIORITY_SHIFT) & GICH_V2_LR_PRIORITY_MASK; lr_reg->state = (lrv >> GICH_V2_LR_STATE_SHIFT) & GICH_V2_LR_STATE_MASK; - lr_reg->hw_status = (lrv >> GICH_V2_LR_HW_SHIFT) & GICH_V2_LR_HW_MASK; + lr_reg->hw_status = lrv & GICH_V2_LR_HW; } static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) @@ -480,9 +480,10 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) ((uint32_t)(lr_reg->priority & GICH_V2_LR_PRIORITY_MASK) << GICH_V2_LR_PRIORITY_SHIFT) | ((uint32_t)(lr_reg->state & GICH_V2_LR_STATE_MASK) - << GICH_V2_LR_STATE_SHIFT) | - ((uint32_t)(lr_reg->hw_status & GICH_V2_LR_HW_MASK) - << GICH_V2_LR_HW_SHIFT)); + << GICH_V2_LR_STATE_SHIFT) ); + + if ( lr_reg->hw_status ) + lrv |= GICH_V2_LR_HW; writel_gich(lrv, GICH_LR + lr * 4); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 0dfa1a1e08..f761ae60d6 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1011,7 +1011,7 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) lr_reg->priority = (lrv >> ICH_LR_PRIORITY_SHIFT) & ICH_LR_PRIORITY_MASK; lr_reg->state = (lrv >> ICH_LR_STATE_SHIFT) & ICH_LR_STATE_MASK; - lr_reg->hw_status = (lrv >> ICH_LR_HW_SHIFT) & ICH_LR_HW_MASK; + lr_reg->hw_status = lrv & ICH_LR_HW; } static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) @@ -1021,8 +1021,10 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) lrv = ( ((u64)(lr->pirq & ICH_LR_PHYSICAL_MASK) << ICH_LR_PHYSICAL_SHIFT)| ((u64)(lr->virq & ICH_LR_VIRTUAL_MASK) << ICH_LR_VIRTUAL_SHIFT) | ((u64)(lr->priority & ICH_LR_PRIORITY_MASK) << ICH_LR_PRIORITY_SHIFT)| - ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) | - ((u64)(lr->hw_status & ICH_LR_HW_MASK) << ICH_LR_HW_SHIFT) ); + ((u64)(lr->state & ICH_LR_STATE_MASK) << ICH_LR_STATE_SHIFT) ); + + if ( lr->hw_status ) + lrv |= ICH_LR_HW; /* * When the guest is using vGICv3, all the IRQs are Group 1. Group 0 diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 1eb08b856e..daec51499c 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -210,7 +210,7 @@ struct gic_lr { uint32_t virq; uint8_t priority; uint8_t state; - uint8_t hw_status; + bool hw_status; }; enum gic_version {