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[209.132.180.67]) by mx.google.com with ESMTP id 31-v6si1115343pli.653.2018.03.20.01.00.37; Tue, 20 Mar 2018 01:00:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qug8WjDy; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751873AbeCTIAg (ORCPT + 11 others); Tue, 20 Mar 2018 04:00:36 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:42077 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751527AbeCTIAg (ORCPT ); Tue, 20 Mar 2018 04:00:36 -0400 Received: by mail-pl0-f68.google.com with SMTP id w15-v6so512448plq.9 for ; Tue, 20 Mar 2018 01:00:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hzV4I9gWFqxQKQqmwVNTsvAO/759WXRXIVI7yRnhB+8=; b=Qug8WjDygyXrUYXrtV9CfnrgjZlhq9blXJrutuZzSC2BsEeWKjXV3ApmSHADAsvn3b RiyI2SmF27vXb//vFGgrJ3bVdts5SYdAcWi8aGUEyVmd9nDowozt8tLLNDhUV8cyjfzm 09vNki8twXPBMtGwKyzuF9Vz80cFWtK+pCEpQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hzV4I9gWFqxQKQqmwVNTsvAO/759WXRXIVI7yRnhB+8=; b=iFxeVQVqgsa9beyxPfX7PLgUUqr3wlJruIGrc+UTnvZRcO3IFcbMZXax5GdBijFZBv ZD/REi2+oTOC0YCNoVJyRZctYbbh9RCSsLsRdRE8fAg08GOzKzzz8lMzO2IxMGRoiD4x +syH+P4rQftsLgH7ENCCaDqy1Xad3E7RC2BK0eyXRnQaLU+eoyZkwtLSyMqlSlF9ExSb ellD0lvWDR1qMjnxZj0tWw+01SBH6sIGqgHQRdVXP1LOC1XrPrPWc6PiLuzEIPqME+Qw kPTlUfaIUgzzsW4Yy8dvhHf7SBws0I8K6/HPTNtPOfolXG683bvJzxdNU/4g0fgtE8Bb zimg== X-Gm-Message-State: AElRT7FGSCQ1ZXOKi9RpREC+sq8UlFgEBt+SjXCcldPygta9Aug4453S C10cAOJQX2x3siGZoJsm54xXMoTXIws= X-Received: by 2002:a17:902:6b81:: with SMTP id p1-v6mr15674459plk.181.1521532835394; Tue, 20 Mar 2018 01:00:35 -0700 (PDT) Received: from localhost ([218.255.99.6]) by smtp.gmail.com with ESMTPSA id z85sm2329407pfd.104.2018.03.20.01.00.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 20 Mar 2018 01:00:34 -0700 (PDT) From: Sam Protsenko To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , Praneeth Bajjuri , Sekhar Nori , Roger Quadros , Tero Kristo , Milosz Wasilewski , Dan Rue Subject: [PATCH 2/3] ARM: OMAP2+ hwmod: Allow modules to disable HW_AUTO Date: Tue, 20 Mar 2018 16:00:26 +0800 Message-Id: <20180320080027.8948-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.16.1 In-Reply-To: <20180320080027.8948-1-semen.protsenko@linaro.org> References: <20180320080027.8948-1-semen.protsenko@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Roger Quadros commit 8ff42da411474893ae373d4280ea88954fa97fcc upstream. Introduce HWMOD_CLKDM_NOAUTO flag that allows the hwmod's clockdomain to be prevented from HW_AUTO while the hwmod is active. This is needed to workaround some modules which don't function correctly with HW_AUTO. e.g. DCAN on DRA7. Signed-off-by: Roger Quadros [nsekhar@ti.com: rebased to v4.9 kernel] Signed-off-by: Sekhar Nori Signed-off-by: Tony Lindgren Signed-off-by: Sam Protsenko --- arch/arm/mach-omap2/omap_hwmod.c | 9 +++++++-- arch/arm/mach-omap2/omap_hwmod.h | 5 +++++ 2 files changed, 12 insertions(+), 2 deletions(-) -- 2.16.1 diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index c1c0fda2f71e..32dcfca42fca 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2155,7 +2155,7 @@ static int _enable(struct omap_hwmod *oh) r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : -EINVAL; - if (oh->clkdm) + if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO)) clkdm_allow_idle(oh->clkdm); if (!r) { @@ -2212,7 +2212,12 @@ static int _idle(struct omap_hwmod *oh) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); - if (oh->clkdm) + /* + * If HWMOD_CLKDM_NOAUTO is set then we don't + * deny idle the clkdm again since idle was already denied + * in _enable() + */ + if (oh->clkdm && !(oh->flags & HWMOD_CLKDM_NOAUTO)) clkdm_deny_idle(oh->clkdm); if (oh->flags & HWMOD_BLOCK_WFI) diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 7c7a31169475..f772f6c77125 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -527,6 +527,10 @@ struct omap_hwmod_omap4_prcm { * operate and they need to be handled at the same time as the main_clk. * HWMOD_NO_IDLE: Do not idle the hwmod at all. Useful to handle certain * IPs like CPSW on DRA7, where clocks to this module cannot be disabled. + * HWMOD_CLKDM_NOAUTO: Allows the hwmod's clockdomain to be prevented from + * entering HW_AUTO while hwmod is active. This is needed to workaround + * some modules which don't function correctly with HW_AUTO. For example, + * DCAN on DRA7x SoC needs this to workaround errata i893. */ #define HWMOD_SWSUP_SIDLE (1 << 0) #define HWMOD_SWSUP_MSTANDBY (1 << 1) @@ -544,6 +548,7 @@ struct omap_hwmod_omap4_prcm { #define HWMOD_RECONFIG_IO_CHAIN (1 << 13) #define HWMOD_OPT_CLKS_NEEDED (1 << 14) #define HWMOD_NO_IDLE (1 << 15) +#define HWMOD_CLKDM_NOAUTO (1 << 16) /* * omap_hwmod._int_flags definitions