diff mbox series

[for-2.12,3/4] target/arm: Set FSR for BKPT, BRK when raising exception

Message ID 20180320134114.30418-4-peter.maydell@linaro.org
State Superseded
Headers show
Series Fix various BRK/BKPT related bugs | expand

Commit Message

Peter Maydell March 20, 2018, 1:41 p.m. UTC 
Now that we have a helper function specifically for the BRK and
BKPT instructions, we can set the exception.fsr there rather
than in arm_cpu_do_interrupt_aarch32(). This allows us to
use our new arm_debug_exception_fsr() helper.

In particular this fixes a bug where we were hardcoding the
short-form IFSR value, which is wrong if the target exception
level has LPAE enabled.

Fixes: https://bugs.launchpad.net/qemu/+bug/1756927
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 target/arm/helper.c    | 1 -
 target/arm/op_helper.c | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

-- 
2.16.2

Comments

Philippe Mathieu-Daudé March 22, 2018, 8:23 a.m. UTC | #1 
On 03/20/2018 10:41 AM, Peter Maydell wrote:
> Now that we have a helper function specifically for the BRK and

> BKPT instructions, we can set the exception.fsr there rather

> than in arm_cpu_do_interrupt_aarch32(). This allows us to

> use our new arm_debug_exception_fsr() helper.

> 

> In particular this fixes a bug where we were hardcoding the

> short-form IFSR value, which is wrong if the target exception

> level has LPAE enabled.

> 

> Fixes: https://bugs.launchpad.net/qemu/+bug/1756927

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


> ---

>  target/arm/helper.c    | 1 -

>  target/arm/op_helper.c | 2 ++

>  2 files changed, 2 insertions(+), 1 deletion(-)

> 

> diff --git a/target/arm/helper.c b/target/arm/helper.c

> index 09893e3f72..dcb8476d9e 100644

> --- a/target/arm/helper.c

> +++ b/target/arm/helper.c

> @@ -7910,7 +7910,6 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)

>          offset = 0;

>          break;

>      case EXCP_BKPT:

> -        env->exception.fsr = 2;

>          /* Fall through to prefetch abort.  */

>      case EXCP_PREFETCH_ABORT:

>          A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);

> diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c

> index 75efff9edf..8e1e521193 100644

> --- a/target/arm/op_helper.c

> +++ b/target/arm/op_helper.c

> @@ -488,6 +488,8 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,

>   */

>  void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)

>  {

> +    /* FSR will only be used if the debug target EL is AArch32. */

> +    env->exception.fsr = arm_debug_exception_fsr(env);

>      raise_exception(env, EXCP_BKPT, syndrome, arm_debug_target_el(env));

>  }

>  

>
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 09893e3f72..dcb8476d9e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7910,7 +7910,6 @@  static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
         offset = 0;
         break;
     case EXCP_BKPT:
-        env->exception.fsr = 2;
         /* Fall through to prefetch abort.  */
     case EXCP_PREFETCH_ABORT:
         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 75efff9edf..8e1e521193 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -488,6 +488,8 @@  void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
  */
 void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome)
 {
+    /* FSR will only be used if the debug target EL is AArch32. */
+    env->exception.fsr = arm_debug_exception_fsr(env);
     raise_exception(env, EXCP_BKPT, syndrome, arm_debug_target_el(env));
 }