From patchwork Wed Mar 21 16:32:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132216 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356047ljb; Wed, 21 Mar 2018 09:34:59 -0700 (PDT) X-Google-Smtp-Source: AG47ELsXAFDcDYyOrDG8Sb651pTN1+Ka4dXMIfwe2O53Cpx+rsJQYApSRCGE5rHXaKV7JO/ZLa0x X-Received: by 10.107.55.133 with SMTP id e127mr20504618ioa.138.1521650099087; Wed, 21 Mar 2018 09:34:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650099; cv=none; d=google.com; s=arc-20160816; b=cuOFQjqQb23jkorlhFBe9djorZQHfR7r33h+2HniMyikNxt/5kE7pyRF4gtWkxDOGf 5gdmUnmex0ZJb7N7I1YgKdjfehIPJxF747LWC0OuLIdV2k2AWidEMIonNHpBb+qdn6ZN AxIirfko9js+LHySJK5D7ScfJ31Caop0TBNLKmP0SbkeqqO7vvk8gYdWzvXRYgZypVT2 6HQCXYweKdRR6BxxRour0VttVXOo+Qy/S8x+fyLNSi/+cvJrc9+7/x7xYSOCxFlBXNIB 7JE8nSUhWMBAdQsIF7WQsxAnG0PYqUJVrkSDO2+AESOy+D41TOrcQMaja3AroH/ccBi4 wiZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=BZ3MWym13TGJpSokA0vMAWmr4yER79IKZ0c9N5ceyYY=; b=ts0vPGK56ChDCPd8VXiWAi3i3GbBQAOPnQ7cQbO6wBz0FNAeio5Ly/ziRJf1yRA1bC oAu2R0F5PINweZOft71WMgUFoFaDzB6b2ptLfSa2P9SRMSi6qNQBIM1bPjx/YoJU9w4Y rC+PFX1dRdzt0F7NYq2nJa+kaYmw8HIsSm6ZyL1gc723zdaOxNxyY3lI15ZY1PLLmDbf itBMQxkXqiRb7aeLd3q6eP4CMvEBez0kqg+DUPKZpEyTYbJpFbQRiv7y+gTRjjgcICuj UUecmmxtgR6fnBTe/mQ5K8zEs873T7gMzB9y2kXYz4mJMJKV3jDwrVRgyeAZytuNPhlY sdpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ia0MCwvZ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id d65si1284082ioj.247.2018.03.21.09.34.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Mar 2018 09:34:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ia0MCwvZ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eygg0-0002to-PI; Wed, 21 Mar 2018 16:33:24 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eygfx-0002mF-KR for xen-devel@lists.xenproject.org; Wed, 21 Mar 2018 16:33:21 +0000 X-Inumbo-ID: 87bb249e-2d25-11e8-9728-bc764e045a96 Received: from mail-wm0-x241.google.com (unknown [2a00:1450:400c:c09::241]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 87bb249e-2d25-11e8-9728-bc764e045a96; Wed, 21 Mar 2018 17:33:05 +0100 (CET) Received: by mail-wm0-x241.google.com with SMTP id t7so10892298wmh.5 for ; Wed, 21 Mar 2018 09:33:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LkujWCqMvdwpsDVsgWdQu8lYVvTKi6jlsEADI9EkNkY=; b=ia0MCwvZcbi4rKBgoGy3IwAzuy6FHyTfLAKJdzo3rg+7zPEoil5LYqFzfoAjdGNX9X tF4cgKK3BQKUjOn54IvaCrUCCxhrHq1D/TZPYXmbKeReN1a1fMBs7zIT3DAOLkT2BiFK n9mlQIHigdOUdYF+xBG/WY7rHVnMZHzMU0bw8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LkujWCqMvdwpsDVsgWdQu8lYVvTKi6jlsEADI9EkNkY=; b=EHTmAvjCovsu5isEXucxqTHXvnjxKxeEJl0Ip/pcyt2vgzEbyH7P5jnfAH6IjFxw7v TQOYGtmK+ZeWnRFb5ot+wZpxHx68bkAUUwKqr9ZBevh6oXpMGMjxWCgtHH9vl/6bq0U0 70REIwuU1Mj0ikiQYhnyhRqQPIYr5JYQpoMqX+NbZokN9bvNXe38B9tECOMWeKbqmYNK stUknj44U+XITk13JjcKk7XQRK6XHldxDe3oDng1Pj46umBwIQogP3FWkKxZmXd4Opet DuHGUXptWO10HyThXuxZf+wKNB3l8+BQHbqjDu06WseX6vyANOcrQTp/lFd5z6OAF6u0 Jwrg== X-Gm-Message-State: AElRT7Et1O/XLSk+sYD5Ogkt4YJTeyoCCpzucfVBYiHrzrmxBpUpcjnJ a6fdcFTdqtCaPWU2DTlrjUKCXw== X-Received: by 10.28.144.134 with SMTP id s128mr2965541wmd.4.1521649999182; Wed, 21 Mar 2018 09:33:19 -0700 (PDT) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:18 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:25 +0000 Message-Id: <20180321163235.12529-30-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 29/39] ARM: new VGIC: Handle virtual IRQ allocation/reservation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To find an unused virtual IRQ number Xen uses a scheme to track used virtual IRQs. Implement this interface in the new VGIC to make the Xen core/arch code happy. This is actually somewhat VGIC agnostic, so is mostly a copy of the code from the old VGIC. But it has to live in the VGIC files, so we can't easily reuse the existing implementation. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 3d818a98ad..8aaad4bffa 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -722,6 +722,50 @@ bool vgic_evtchn_irq_pending(struct vcpu *v) return pending; } +bool vgic_reserve_virq(struct domain *d, unsigned int virq) +{ + if ( virq >= vgic_num_irqs(d) ) + return false; + + return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs); +} + +int vgic_allocate_virq(struct domain *d, bool spi) +{ + int first, end; + unsigned int virq; + + if ( !spi ) + { + /* We only allocate PPIs. SGIs are all reserved */ + first = 16; + end = 32; + } + else + { + first = 32; + end = vgic_num_irqs(d); + } + + /* + * There is no spinlock to protect allocated_irqs, therefore + * test_and_set_bit may fail. If so retry it. + */ + do + { + virq = find_next_zero_bit(d->arch.vgic.allocated_irqs, end, first); + if ( virq >= end ) + return -1; + } while ( test_and_set_bit(virq, d->arch.vgic.allocated_irqs) ); + + return virq; +} + +void vgic_free_virq(struct domain *d, unsigned int virq) +{ + clear_bit(virq, d->arch.vgic.allocated_irqs); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) {