| Message ID | 1521781901-20466-1-git-send-email-hayashi.kunihiko@socionext.com |
|---|---|
| State | Accepted |
| Commit | c2fd8756c5c3a3187094a4e7d7a6c87aa8033901 |
| Headers | show |
| Series | clk: uniphier: add ethernet clock control support for PXs3 | expand |
2018-03-23 14:11 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>: > Add clock control for ethernet controller on PXs3 SoC. > > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > --- > drivers/clk/uniphier/clk-uniphier-sys.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c > index d244e72..faadd9b 100644 > --- a/drivers/clk/uniphier/clk-uniphier-sys.c > +++ b/drivers/clk/uniphier/clk-uniphier-sys.c > @@ -233,6 +233,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { > UNIPHIER_LD20_SYS_CLK_SD, > UNIPHIER_LD11_SYS_CLK_NAND(2), > UNIPHIER_LD11_SYS_CLK_EMMC(4), > + UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9), > + UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10), > UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */ > UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */ > UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */ > -- Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> -- Best Regards Masahiro Yamada
Quoting Kunihiko Hayashi (2018-03-22 22:11:41) > Add clock control for ethernet controller on PXs3 SoC. > > Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> > --- Applied to clk-next
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index d244e72..faadd9b 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -233,6 +233,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { UNIPHIER_LD20_SYS_CLK_SD, UNIPHIER_LD11_SYS_CLK_NAND(2), UNIPHIER_LD11_SYS_CLK_EMMC(4), + UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9), + UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10), UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */ UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */ UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
Add clock control for ethernet controller on PXs3 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> --- drivers/clk/uniphier/clk-uniphier-sys.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.7.4