From patchwork Fri Mar 23 12:57:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 132329 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp558369ljb; Fri, 23 Mar 2018 05:57:09 -0700 (PDT) X-Google-Smtp-Source: AG47ELvuZadkxoOcq4Ce4CaZhG0uT2rbqclho6JQ8kCR3+9T8/6I2hMmCXwTBw369f7ndRt+C6Hl X-Received: by 10.99.127.75 with SMTP id p11mr20465431pgn.392.1521809829261; Fri, 23 Mar 2018 05:57:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521809829; cv=none; d=google.com; s=arc-20160816; b=sZKJpU58SqGPMJzyF/nedhB0lZPVfqG8bgeo+jz9h4POSeAtiGaQreLzx9a73CrngC rnRLdxcSIUXx/YUMnwSGdvCKHdBxDqXV1FVLDPYA0BaeE312FWMN+jQQw4DGm0KDLWKX HXri+aKm7/pt/fUudefQuUZ3WxcGglTns1kqO4Mn5nqDlfFgchHq9y4qAeJmvY5ZGnxE 2kcOpAT5VUOkixs/LjF++OAJ2YosSuMd/5jpxK6UZ8JE+k54e8MiR8OPlFUKPt+gwyWk l+YEfnGLv5pwI0OStoMhiVwu9KENrWyNlkEgPbIfCdyttBzNVfdC72hxLcLfBglF73EA InaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:cc:list-subscribe :list-help:list-post:list-archive:list-unsubscribe:list-id :precedence:mime-version:message-id:date:subject:to:from :dkim-signature:delivered-to:arc-authentication-results; bh=OW2NkGPeYI9Mv7o9jMI4MrfXu2N2/DDawGwBfvtddHE=; b=fZ9UxXkN2LtXRKswGUxTPOv0h07kZkV5Y3pO1oSF+kvI+4PCIU6skbqmyx3ED3KdcL UldHYeXpL0LDbZ/FnYWtv2RFq9wz8cMF+kPUd30Bwo4opPfvWgeAXnFC9U8Ymnb0uLlC d4eQpQ3z17tl2IqoD0WB8aRkQ1ZwKm6Wsy4/gKrZJG8XL3cM1/CPlL5vOB97OKZro1CO rTzQirGRHAMNhdRdcrVE3JgXkHh1kLlF30A3DfkVTjDwXdUIUbBfx9fXZOiw0LjW9tXh GV3ZMUycqdSak5ExFRQk30mYZ2J4diOx0jhZUt+ksHqLWEeiWiwgGhholKOjkbwQut1Z gu4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=d3gVPaIT; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTPS id 200si3392269pge.570.2018.03.23.05.57.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 23 Mar 2018 05:57:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=d3gVPaIT; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CE036E371; Fri, 23 Mar 2018 12:57:07 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47D0A6E323 for ; Fri, 23 Mar 2018 12:57:05 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w2NCv2PL030881; Fri, 23 Mar 2018 07:57:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1521809822; bh=BxZhmiWvPH12UN8fBzfejFAtxxVGSrwuO4mAFlSrqN4=; h=From:To:CC:Subject:Date; b=d3gVPaITyIcfZvmSHLLej3XvdaGezMSepfst35T5pDfa7ctJcMI/uAXCDh6XuiDip XEg8GeY6grIUZNIW0sAw5y8UH8Yd9o1GU0sICFchm5aZZ+gdT9R3fb05SUoAp+H132 Dp31h4etWBWJb79xtjUmAv91l59yiekDxZiY2//8= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w2NCv2bY003926; Fri, 23 Mar 2018 07:57:02 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Fri, 23 Mar 2018 07:57:01 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Fri, 23 Mar 2018 07:57:01 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w2NCuxH4026301; Fri, 23 Mar 2018 07:57:00 -0500 From: Peter Ujfalusi To: , Subject: [PATCH] drm/omap: fix memory barrier bug in DMM driver Date: Fri, 23 Mar 2018 14:57:07 +0200 Message-ID: <20180323125707.25223-1-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.16.3 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jsarha@ti.com, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Tomi Valkeinen A DMM timeout "timed out waiting for done" has been observed on DRA7 devices. The timeout happens rarely, and only when the system is under heavy load. Debugging showed that the timeout can be made to happen much more frequently by optimizing the DMM driver, so that there's almost no code between writing the last DMM descriptors to RAM, and writing to DMM register which starts the DMM transaction. The current theory is that a wmb() does not properly ensure that the data written to RAM is observable by all the components in the system. This DMM timeout has caused interesting (and rare) bugs as the error handling was not functioning properly (the error handling has been fixed in previous commits): * If a DMM timeout happened when a GEM buffer was being pinned for display on the screen, a timeout error would be shown, but the driver would continue programming DSS HW with broken buffer, leading to SYNCLOST floods and possible crashes. * If a DMM timeout happened when other user (say, video decoder) was pinning a GEM buffer, a timeout would be shown but if the user handled the error properly, no other issues followed. * If a DMM timeout happened when a GEM buffer was being released, the driver does not even notice the error, leading to crashes or hang later. This patch adds wmb() and readl() calls after the last bit is written to RAM, which should ensure that the execution proceeds only after the data is actually in RAM, and thus observable by DMM. The read-back should not be needed. Further study is required to understand if DMM is somehow special case and read-back is ok, or if DRA7's memory barriers do not work correctly. Signed-off-by: Tomi Valkeinen Signed-off-by: Peter Ujfalusi --- drivers/gpu/drm/omapdrm/omap_dmm_tiler.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c index c40f90d2db82..27c67bc36203 100644 --- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c +++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c @@ -410,6 +410,17 @@ static int dmm_txn_commit(struct dmm_txn *txn, bool wait) } txn->last_pat->next_pa = 0; + /* ensure that the written descriptors are visible to DMM */ + wmb(); + + /* + * NOTE: the wmb() above should be enough, but there seems to be a bug + * in OMAP's memory barrier implementation, which in some rare cases may + * cause the writes not to be observable after wmb(). + */ + + /* read back to ensure the data is in RAM */ + readl(&txn->last_pat->next_pa); /* write to PAT_DESCR to clear out any pending transaction */ dmm_write(dmm, 0x0, reg[PAT_DESCR][engine->id]);