From patchwork Tue Mar 27 17:47:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 132489 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp5371406ljb; Tue, 27 Mar 2018 10:47:52 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/hgiMPg29Wmt1KKPydgOqE9lAA6Y3rVWidN7p6hiyS1YMZsY15V9qYOpRrVn52eiaIqKg5 X-Received: by 2002:a17:902:8f8b:: with SMTP id z11-v6mr279478plo.316.1522172872395; Tue, 27 Mar 2018 10:47:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522172872; cv=none; d=google.com; s=arc-20160816; b=S/uQS6iqsmv1OWDhEXk9eY60kx3oirCVYiM6ULCkP4vwSzIoRhl4NrnXm+5PBUNtzO dDDkHpaXQHw2F6PzRRa1VyJwEzWvHSkNnxeqwZbzPhUHmHWcEqdBVkSIZsH68J9FhTWh ME6cq2HLkPfeMO+PczbZdjqXfwaNgwCrKV68hkPeDzxf/lzUxj2tBRNPUTAUbZbghp7h 4KZmOKMjF9jGzjQ5PfyoOc0hFZ1ol+aQuFZ+tWHk5y06d7RQEM0yjgegiFEc+HC0q5OF JoHZmmm0/m2SE3Em6QbEkABhbGX6Tzd+rb4Z8pXE5o9R/pfnfiz/Px+r6dJv2LROkOui qEwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature:arc-authentication-results; bh=qGavB7HisKrniz0v1H+n4/604LULa8SRD8Qm3mXZWqA=; b=eu28ntw2raQVUcTPkZ31KhGablLPoFNcpLIcXgE+hW5siqHRIXl7wq35TNRk1WN8WY CYlFr91Gy1X1SMKStSlUMfwKj+3Zq5XS+EmmgRppog1s1KSl+Q2QpqSGkBAf+bOfbQfa tzzf2UqdmCr48FEiP6LLFNfr9tu3A7THUdIy+XCuzsWMUkcQ604BoJDV4W8Z0UJHrXEj qfixYaBCFLZypN2JDrkNMz8VBr3FLl3XBbjpsOSqHmSerT5wZn4Mu1UTUE6ad/BHzW1A f7cWwmiDKUX6z7C5wRZbJHzG7OLWwU6MnDH8vsZY+swP1tvPgIqbtNfkdJSke/iGZjXo iEzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=aatlpOVg; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o6-v6si1625079plk.746.2018.03.27.10.47.52; Tue, 27 Mar 2018 10:47:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=aatlpOVg; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752027AbeC0Rrt (ORCPT + 5 others); Tue, 27 Mar 2018 13:47:49 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:36748 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750880AbeC0Rrs (ORCPT ); Tue, 27 Mar 2018 13:47:48 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w2RHlS6T026013; Tue, 27 Mar 2018 12:47:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1522172848; bh=LdogqPbd0q376H9x/BfqwZI5AhJws9IXuEDnXgRSmRQ=; h=From:To:CC:Subject:Date; b=aatlpOVg8I0/b2UX2wVi1CpMLPV68p8t4F04irtIucUYzefDa3p7njdeZXeuq4Qq2 45CLW+NRQ5dGgaYHlwF9XDye0rGlo+iu2CtzjtwIdx7TOno6JGI13wmtY/wQHzWVQU WRfO8iD5y2TeKPzhxjL1aA+kcBBYCKXqWSg+JSlA= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w2RHlS6h015322; Tue, 27 Mar 2018 12:47:28 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 27 Mar 2018 12:47:27 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 27 Mar 2018 12:47:27 -0500 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w2RHlPWE013486; Tue, 27 Mar 2018 12:47:25 -0500 From: Tero Kristo To: , , , , CC: , Subject: [PATCH] clk: ti: fix flag space conflict with clkctrl clocks Date: Tue, 27 Mar 2018 20:47:04 +0300 Message-ID: <1522172824-14094-1-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The introduction of support for CLK_SET_RATE_PARENT flag for clkctrl clocks used a generic clock flag, which causes a conflict with the rest of the clkctrl flags, namely the NO_IDLEST flag. This can cause boot failures on certain platforms where this flag is introduced, by omitting the wait for the clockctrl module to be fully enabled before proceeding with rest of the code. Fix this by moving all the clkctrl specific flags to their own bit-range. Signed-off-by: Tero Kristo Fixes: 49159a9dc3da ("clk: ti: add support for CLK_SET_RATE_PARENT flag") Reported-by: Christophe Lyon --- drivers/clk/ti/clock.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Tested-by: Tony Lindgren diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index 90b86aa..b582780 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -76,6 +76,11 @@ enum { #define CLKF_CORE (1 << 9) #define CLKF_J_TYPE (1 << 10) +/* CLKCTRL flags */ +#define CLKF_SW_SUP BIT(5) +#define CLKF_HW_SUP BIT(6) +#define CLKF_NO_IDLEST BIT(7) + #define CLK(dev, con, ck) \ { \ .lk = { \ @@ -185,10 +190,6 @@ struct omap_clkctrl_data { extern const struct omap_clkctrl_data dm814_clkctrl_data[]; extern const struct omap_clkctrl_data dm816_clkctrl_data[]; -#define CLKF_SW_SUP BIT(0) -#define CLKF_HW_SUP BIT(1) -#define CLKF_NO_IDLEST BIT(2) - typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,