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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id s196si8528763qke.94.2018.04.06.08.22.06 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 06 Apr 2018 08:22:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:34016 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f4TBm-0006va-BB for patch@linaro.org; Fri, 06 Apr 2018 11:22:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f4T8q-0004On-G2 for qemu-devel@nongnu.org; Fri, 06 Apr 2018 11:19:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f4T8n-0004hO-8a for qemu-devel@nongnu.org; Fri, 06 Apr 2018 11:19:04 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:23918 helo=mx07-00178001.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f4T8m-0004h4-UI for qemu-devel@nongnu.org; Fri, 06 Apr 2018 11:19:01 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w36FF60w018365; Fri, 6 Apr 2018 17:18:59 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2h1yf7prat-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 06 Apr 2018 17:18:59 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3221831; Fri, 6 Apr 2018 15:18:59 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 17188A6EA; Fri, 6 Apr 2018 15:18:59 +0000 (GMT) Received: from gnx2104.gnb.st.com (10.75.127.51) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 6 Apr 2018 17:18:58 +0200 From: Christophe Lyon To: , , Date: Fri, 6 Apr 2018 17:17:31 +0200 Message-ID: <20180406151752.10854-4-christophe.lyon@st.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180406151752.10854-1-christophe.lyon@st.com> References: <20180406151752.10854-1-christophe.lyon@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG6NODE1.st.com (10.75.127.16) To SFHDAG5NODE1.st.com (10.75.127.13) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-04-06_08:, , signatures=0 X-MIME-Autoconverted: from 8bit to quoted-printable by mx08-.pphosted.com id w36FF60w018365 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 91.207.212.93 Subject: [Qemu-devel] [ARM/FDPIC 3/4] linux-user: ARM-FDPIC: Add support for signals for FDPIC targets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The FDPIC restorer needs to deal with a function descriptor, hence we have to extend 'retcode' such that it can hold the instructions needed to perform this. The restorer sequence uses the same thumbness as the exception handler (mainly to support Thumb-only architectures). Co-Authored-By: Mickaël Guêné Signed-off-by: Christophe Lyon -- 2.6.3 diff --git a/linux-user/signal.c b/linux-user/signal.c index 2ea3e03..75643d7 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -2039,13 +2039,13 @@ struct sigframe_v1 { struct target_sigcontext sc; abi_ulong extramask[TARGET_NSIG_WORDS-1]; - abi_ulong retcode; + abi_ulong retcode[4]; }; struct sigframe_v2 { struct target_ucontext_v2 uc; - abi_ulong retcode; + abi_ulong retcode[4]; }; struct rt_sigframe_v1 @@ -2054,14 +2054,14 @@ struct rt_sigframe_v1 abi_ulong puc; struct target_siginfo info; struct target_ucontext_v1 uc; - abi_ulong retcode; + abi_ulong retcode[4]; }; struct rt_sigframe_v2 { struct target_siginfo info; struct target_ucontext_v2 uc; - abi_ulong retcode; + abi_ulong retcode[4]; }; #define TARGET_CONFIG_CPU_32 1 @@ -2084,6 +2084,23 @@ static const abi_ulong retcodes[4] = { SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN }; +#if defined(CONFIG_USE_FDPIC) +/* + * Stub needed to make sure the FD register (r9) contains the right + * value. + */ +static const unsigned long sigreturn_fdpic_codes[3] = { + 0xe59fc004, /* ldr r12, [pc, #4] to read function descriptor */ + 0xe59c9004, /* ldr r9, [r12, #4] to setup GOT */ + 0xe59cf000 /* ldr pc, [r12] to jump into restorer */ +}; + +static const unsigned long sigreturn_fdpic_thumb_codes[3] = { + 0xc008f8df, /* ldr r12, [pc, #8] to read function descriptor */ + 0x9004f8dc, /* ldr r9, [r12, #4] to setup GOT */ + 0xf000f8dc /* ldr pc, [r12] to jump into restorer */ +}; +#endif static inline int valid_user_regs(CPUARMState *regs) { @@ -2143,7 +2160,19 @@ setup_return(CPUARMState *env, struct target_sigaction *ka, { abi_ulong handler = ka->_sa_handler; abi_ulong retcode; + +#ifdef CONFIG_USE_FDPIC + int thumb; + + if (env->is_fdpic) { + thumb = (((abi_ulong *)g2h(ka->_sa_handler))[0]) & 1; + } else { + thumb = handler & 1; + } +#else int thumb = handler & 1; +#endif + uint32_t cpsr = cpsr_read(env); cpsr &= ~CPSR_IT; @@ -2154,8 +2183,37 @@ setup_return(CPUARMState *env, struct target_sigaction *ka, } if (ka->sa_flags & TARGET_SA_RESTORER) { +#ifdef CONFIG_USE_FDPIC + if (env->is_fdpic) { + /* For FDPIC we ensure that the restorer is called with a + * correct r9 value. For that we need to write code on + * the stack that sets r9 and jumps back to restorer + * value. + */ + if (thumb) { + __put_user(sigreturn_fdpic_thumb_codes[0], rc); + __put_user(sigreturn_fdpic_thumb_codes[1], rc + 1); + __put_user(sigreturn_fdpic_thumb_codes[2], rc + 2); + __put_user((abi_ulong)ka->sa_restorer, rc + 3); + } else { + __put_user(sigreturn_fdpic_codes[0], rc); + __put_user(sigreturn_fdpic_codes[1], rc + 1); + __put_user(sigreturn_fdpic_codes[2], rc + 2); + __put_user((abi_ulong)ka->sa_restorer, rc + 3); + } + + retcode = rc_addr + thumb; + } else +#endif retcode = ka->sa_restorer; } else { +#ifdef CONFIG_USE_FDPIC + if (env->is_fdpic) { + qemu_log_mask(LOG_UNIMP, + "arm: FDPIC signal return not implemented"); + abort(); + } else { +#endif unsigned int idx = thumb; if (ka->sa_flags & TARGET_SA_SIGINFO) { @@ -2165,12 +2223,29 @@ setup_return(CPUARMState *env, struct target_sigaction *ka, __put_user(retcodes[idx], rc); retcode = rc_addr + thumb; +#ifdef CONFIG_USE_FDPIC + } +#endif } env->regs[0] = usig; +#ifdef CONFIG_USE_FDPIC + if (env->is_fdpic) { + env->regs[9] = ((abi_ulong *)g2h(ka->_sa_handler))[1]; + } +#endif env->regs[13] = frame_addr; env->regs[14] = retcode; +#ifdef CONFIG_USE_FDPIC + if (env->is_fdpic) { + env->regs[15] = ((abi_ulong *)g2h(ka->_sa_handler))[0] + & (thumb ? ~1 : ~3); + } else { + env->regs[15] = handler & (thumb ? ~1 : ~3); + } +#else env->regs[15] = handler & (thumb ? ~1 : ~3); +#endif cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); } @@ -2264,7 +2339,7 @@ static void setup_frame_v1(int usig, struct target_sigaction *ka, __put_user(set->sig[i], &frame->extramask[i - 1]); } - setup_return(regs, ka, &frame->retcode, frame_addr, usig, + setup_return(regs, ka, frame->retcode, frame_addr, usig, frame_addr + offsetof(struct sigframe_v1, retcode)); unlock_user_struct(frame, frame_addr, 1); @@ -2286,7 +2361,7 @@ static void setup_frame_v2(int usig, struct target_sigaction *ka, setup_sigframe_v2(&frame->uc, set, regs); - setup_return(regs, ka, &frame->retcode, frame_addr, usig, + setup_return(regs, ka, frame->retcode, frame_addr, usig, frame_addr + offsetof(struct sigframe_v2, retcode)); unlock_user_struct(frame, frame_addr, 1); @@ -2341,7 +2416,7 @@ static void setup_rt_frame_v1(int usig, struct target_sigaction *ka, __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]); } - setup_return(env, ka, &frame->retcode, frame_addr, usig, + setup_return(env, ka, frame->retcode, frame_addr, usig, frame_addr + offsetof(struct rt_sigframe_v1, retcode)); env->regs[1] = info_addr; @@ -2372,7 +2447,7 @@ static void setup_rt_frame_v2(int usig, struct target_sigaction *ka, setup_sigframe_v2(&frame->uc, set, env); - setup_return(env, ka, &frame->retcode, frame_addr, usig, + setup_return(env, ka, frame->retcode, frame_addr, usig, frame_addr + offsetof(struct rt_sigframe_v2, retcode)); env->regs[1] = info_addr;