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[for-2.12] tcg: Introduce tcg_set_insn_start_param

Message ID 20180410003558.2470-1-richard.henderson@linaro.org
State Superseded
Headers show
Series [for-2.12] tcg: Introduce tcg_set_insn_start_param | expand

Commit Message

Richard Henderson April 10, 2018, 12:35 a.m. UTC
The parameters for tcg_gen_insn_start are target_ulong, which may be split
into two TCGArg parameters for storage in the opcode on 32-bit hosts.

Fixes the ARM target and its direct use of tcg_set_insn_param, which would
set the wrong argument in the 64-on-32 case.

Cc: qemu-stable@nongnu.org
Reported-by: alarson@ddci.com
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---

Peter, I'm not sure what the reproducer is for this reported problem.
I could boot my aa64 images both before and after this patch.  Perhaps
I would have needed to run an aa32 binary within the aa64 kernel?


r~

---
 target/arm/translate.h |  2 +-
 tcg/tcg.h              | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

-- 
2.14.3

Comments

Peter Maydell April 10, 2018, 10:49 a.m. UTC | #1
On 10 April 2018 at 01:35, Richard Henderson
<richard.henderson@linaro.org> wrote:
> The parameters for tcg_gen_insn_start are target_ulong, which may be split

> into two TCGArg parameters for storage in the opcode on 32-bit hosts.

>

> Fixes the ARM target and its direct use of tcg_set_insn_param, which would

> set the wrong argument in the 64-on-32 case.

>

> Cc: qemu-stable@nongnu.org

> Reported-by: alarson@ddci.com

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>

> Peter, I'm not sure what the reproducer is for this reported problem.


It's a standalone binary, which was attached to this email:
https://lists.gnu.org/archive/html/qemu-devel/2018-03/msg05995.html

I've checked and this patch does indeed fix it.

Applied to target-arm.next, thanks.

-- PMM
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Patch

diff --git a/target/arm/translate.h b/target/arm/translate.h
index c47febf99d..4428c98e2e 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -120,7 +120,7 @@  static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 
     /* We check and clear insn_start_idx to catch multiple updates.  */
     assert(s->insn_start != NULL);
-    tcg_set_insn_param(s->insn_start, 2, syn);
+    tcg_set_insn_start_param(s->insn_start, 2, syn);
     s->insn_start = NULL;
 }
 
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 9e2d909a4a..30896ca304 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -825,6 +825,16 @@  static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
     op->args[arg] = v;
 }
 
+static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
+{
+#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+    tcg_set_insn_param(op, arg, v);
+#else
+    tcg_set_insn_param(op, arg * 2, v);
+    tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
+#endif
+}
+
 /* The last op that was emitted.  */
 static inline TCGOp *tcg_last_op(void)
 {