[2/4] arm: Fix armv7 neon strcmp on ARM mode

Message ID 1523481378-16290-2-git-send-email-adhemerval.zanella@linaro.org
State New
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  • [1/4] arm: Fix armv7 neon memchr on ARM mode
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Commit Message

Adhemerval Zanella April 11, 2018, 9:16 p.m.
Current optimized armv7 neon strcmp uses the NO_THUMB wrongly to
conditionalize thumb instruction usage.  The flags is meant to be
defined before sysdep.h inclusion and to indicate the assembly
requires to build in ARM mode, not to check whether thumb is
enable or not.  This patch fixes it by using the GCC provided
'__thumb__' instead.

Also, even if the implementation is fixed to not use thumb instructions
it was clearly not proper checked in ARM mode: the 'prepare_mask' does
not build (it sets the 'mvn' instruction to use register predicate in
shift amount).  This patch fixes it by using a S2HI plus mvn to mimic
the expected nor operation.

Checked on arm-linux-gnueabihf (with -marm and -mthumb mode).

	[BZ #23031]
	* sysdeps/arm/armv7/strcmp.S [!__thumb__] (prepare_mask): Fix build
	and logic.
 ChangeLog                  | 4 ++++
 sysdeps/arm/armv7/strcmp.S | 6 +++---
 2 files changed, 7 insertions(+), 3 deletions(-)



diff --git a/sysdeps/arm/armv7/strcmp.S b/sysdeps/arm/armv7/strcmp.S
index 060b865..a20b3e5 100644
--- a/sysdeps/arm/armv7/strcmp.S
+++ b/sysdeps/arm/armv7/strcmp.S
@@ -82,8 +82,7 @@ 
 #define data2		r3
 #define syndrome	tmp2
-#ifndef NO_THUMB
+#ifdef __thumb__
 /* This code is best on Thumb.  */
@@ -97,7 +96,8 @@ 
 /* In ARM code we don't have ORN, but we can use MVN with a register shift.  */
 .macro prepare_mask mask_reg, nbits_reg
-	mvn \mask_reg, const_m1, S2HI \nbits_reg
+	S2HI \mask_reg, const_m1, \nbits_reg
+	mvn \mask_reg, \mask_reg
 .macro apply_mask data_reg, mask_reg
 	orr \data_reg, \data_reg, \mask_reg