From patchwork Thu Apr 12 11:11:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Rutland X-Patchwork-Id: 133218 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp1572055ljb; Thu, 12 Apr 2018 04:13:07 -0700 (PDT) X-Google-Smtp-Source: AIpwx49pDpds/VaHgyyrg9AQ9Gp6JAp46Ig5G9mYWwQs3/HmrVMbgy4BBr7pG2u+2/gK1L3lRq16 X-Received: by 10.101.80.131 with SMTP id r3mr375677pgp.284.1523531587399; Thu, 12 Apr 2018 04:13:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523531587; cv=none; d=google.com; s=arc-20160816; b=KZh7PjjAvYXpxd/XSFZwBbyV5o+2TUtC2ebaVcjjuwVlzrJa0JzY97M564es36ohX1 5oZDIt6UNzQzDC2CxOUPA13zRHHA8v6Btbg1l9CwG0LNC41KohrBOn1/KRcrcHdcXHRz Jf0d+NnQDKs+lg5WL7mUXNkft0zl+t3HCoho3bnDr0PhO6UcIux3ef0sQs5d0WTsUXxO PZNAO7W6FPl8xUn6W/KROiToa+1LOGW1iXZzuNfH6z/LgE+HqUPz3zK21K8ogC4Bqv13 5C2N2FgpqmfI0ubgKHgJ0xsfEpNQHxmwYrqCcnrvuxM1gEhcGTrtA+jpPySeUOF1Zbp2 G1Jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=2r7LAzF6siDZVx58fha92sJRaDkINo1ZU8JS+JPw+Ws=; b=AkxW6l7uOoYGK0eC/V2PAFYYUBlSd6rpQbq6pAVow0YFdaXaA6Z9DOSBWHTou5Gen+ ZABVsL43Lyf1AfvImDgqzkWdH8cVtr0EvSWY0fmVyiLDrbHX9QmOLRf/TDd+QnWYnRV/ J6QJXzJ/WgQS6PQNPJY/44IWqcX0xw/ZD/bpm+FWe/1zn6fyzYTpad6FmEndbKp0/f1O 79JNoYM8iT5bkDZBQ9PYfiiNUIiUv6N6cuJYKsMhzuclE5tkkrEHcB0+dIhjucBYCnsf x9RVIFjzRXPfNbSqXbMhcJ/t032TjQefOxK4rTOEWE8PgMtF22GSj/7avTAYyzBkMNfA 4v0Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bg3-v6si3001807plb.118.2018.04.12.04.13.07; Thu, 12 Apr 2018 04:13:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752450AbeDLLNG (ORCPT + 11 others); Thu, 12 Apr 2018 07:13:06 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:59516 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752125AbeDLLNG (ORCPT ); Thu, 12 Apr 2018 07:13:06 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A3C980D; Thu, 12 Apr 2018 04:13:06 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 56EFE3F24A; Thu, 12 Apr 2018 04:13:04 -0700 (PDT) From: Mark Rutland To: stable@vger.kernel.org Cc: mark.brown@linaro.org, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, will.deacon@arm.com, catalin.marinas@arm.com, ghackmann@google.com, shankerd@codeaurora.org Subject: [PATCH v4.9.y 23/42] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Date: Thu, 12 Apr 2018 12:11:19 +0100 Message-Id: <20180412111138.40990-24-mark.rutland@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180412111138.40990-1-mark.rutland@arm.com> References: <20180412111138.40990-1-mark.rutland@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Will Deacon commit a65d219fe5dc7887fd5ca04c2ac3e9a34feb8dfc upstream. Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon Signed-off-by: Catalin Marinas Signed-off-by: Mark Rutland [v4.9 backport] --- arch/arm64/include/asm/cputype.h | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.11.0 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 1d47930c30dc..9ee3038a6b98 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -75,7 +75,10 @@ #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 +#define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A #define APM_CPU_PART_POTENZA 0x000 @@ -87,6 +90,9 @@ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)