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[81.169.180.215]) by mx.google.com with ESMTP id m28si186799edm.267.2018.04.13.08.33.05; Fri, 13 Apr 2018 08:33:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=UGGo6qQw; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id A8612C21D9A; Fri, 13 Apr 2018 15:31:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B9047C21DEC; Fri, 13 Apr 2018 15:31:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 89FDAC21C2F; Fri, 13 Apr 2018 15:31:25 +0000 (UTC) Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com [209.85.128.193]) by lists.denx.de (Postfix) with ESMTPS id 2A7F1C21C38 for ; Fri, 13 Apr 2018 15:31:25 +0000 (UTC) Received: by mail-wr0-f193.google.com with SMTP id y7so9150860wrh.10 for ; Fri, 13 Apr 2018 08:31:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CA2atoKRAAeZaRXet7yXYeavk5dzsuMokIvwFjiBCMU=; b=UGGo6qQw9Xs9ezSaaihDumk2CfEOspuADg0qeEHohW9WKQ7JtET023nWSXTL/JB4GS sLqwOxflB1e6GnGmGHmW/KK8M57BWgl6dyZiVzSYiEJCAP7MS4LEo/6P+odWLrATDSYH 7E6V/EM2e6gpiwNeH06fPbFANJESG1XxLpgXs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CA2atoKRAAeZaRXet7yXYeavk5dzsuMokIvwFjiBCMU=; b=MwbtIz3JVfhuCMjND6RNZOquCjE6g1P+sba7KOJZz6KeCZjm2SpD249ceIrOOpWwzD cFWmDFhRCw+hjN5xlAeUFdduos4BXi1dO0M4of1GOy2FB3KI/a7HHGzUT3uVcS7TfyB+ YTCVTpnRXKYnOxSyi4/UgVMAFppGvCUYb8LY9LQi9g9dqyiP6NOBWfZap+WtUq/g/nHl OHP3DgZHSPF7RzmDsRPI7NP/2zkhRGSs2JttTuLGxlu5OipkRwLWOSJceYCfQSSmd/Aw WIz727TZuzNKUH3jltWORf8YDZeKnCWFZtssuK3J4ZWL61l8/Mchln7Fr1SkI3TuPwJS cQjg== X-Gm-Message-State: ALQs6tApcKF3TkRBRZJPARKJ9w4qPZ9Lbl9gTn9YtQ9gfO+isCXSPncn gtYZCNPSwQDlZPNMcGa5TLl/g8KEYRM= X-Received: by 10.80.211.3 with SMTP id g3mr20685782edh.15.1523633484648; Fri, 13 Apr 2018 08:31:24 -0700 (PDT) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id x35sm3516008edx.86.2018.04.13.08.31.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Apr 2018 08:31:24 -0700 (PDT) From: Bryan O'Donoghue To: u-boot@lists.denx.de, fabio.estevam@nxp.com, sbabic@denx.de Date: Fri, 13 Apr 2018 16:31:05 +0100 Message-Id: <1523633481-20914-2-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523633481-20914-1-git-send-email-bryan.odonoghue@linaro.org> References: <1523633481-20914-1-git-send-email-bryan.odonoghue@linaro.org> Cc: breno.lima@nxp.com, Utkarsh Gupta , rui.silva@linaro.org, paul.liu@linaro.org Subject: [U-Boot] [PATCH v3 01/17] imximage: Specify default IVT offset in IMX image X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds BOOTROM_IVT_HDR_OFFSET at 0xC00. The BootROM expects to find the IVT header at a particular offset in an i.MX image. Defining the expected offset of the IVT header in the first-stage BootROM image format is of use of later stage authentication routines where those routines continue to follow the first-stage authentication layout. This patch defines the first stage offset which later patch make use of. Signed-off-by: Bryan O'Donoghue Cc: Utkarsh Gupta Cc: Breno Lima Cc: Fabio Estevam --- include/imximage.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/imximage.h b/include/imximage.h index 553b852..800fd63 100644 --- a/include/imximage.h +++ b/include/imximage.h @@ -14,6 +14,9 @@ #define APP_CODE_BARKER 0xB1 #define DCD_BARKER 0xB17219E9 +/* Specify the offset of the IVT in the IMX header as expected by BootROM */ +#define BOOTROM_IVT_HDR_OFFSET 0xC00 + /* * NOTE: This file must be kept in sync with arch/arm/include/asm/\ * mach-imx/imximage.cfg because tools/imximage.c can not