From patchwork Tue Apr 17 14:43:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramon Fried X-Patchwork-Id: 133549 Delivered-To: patch@linaro.org Received: by 10.46.84.18 with SMTP id i18csp4803282ljb; Tue, 17 Apr 2018 07:49:32 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/xmfNb84aDtfVm+y4QPT4tTt1+c5wMc2qY+Ov8cQffdQLFZPThverbHu3mc5xATm2HhsfA X-Received: by 10.80.234.139 with SMTP id d11mr3566360edo.7.1523976572460; Tue, 17 Apr 2018 07:49:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523976572; cv=none; d=google.com; s=arc-20160816; b=KB/oIIyYAum7CA08nPwWQj92RNsOv+8gzFzDx548MiKhAWENodZLeiSsT/9TAs4Tvq sXDGhzaCnk4pThiOMfg7cEbN/E9aLiig5Tl7i9TnWqKcvNez85Hp2m2+F47R8kvnOn8k JgplZIATAAr4FP3apNIaMUj8O4t0Ljnc2VQuoVzxiAtmOdJ3jr0XfEoR1iZDn1T6Xg1F N5akXaEaG+KAKpHHttt8iauDn0ZTgbNiC2oTBq5IKlS6GYMYS5zW2+9nc7vGU1PU+m3w 0LRzI2R3ZpQsGFE0KeatCReDSQ7jrXVwtqQWhNHsWEoCauCkKgU17j9ecmpj32Pv4tpO CtlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=SJvnH2gySrb+UxfX8KEDfHvgNIt83/BZgX8h1Y/BhZU=; b=CU0fnFRF01Hx/QQbErwiTnZuinoYIDDbK5VeLaG3DM5ntYDBU593p9h41JL41eGnKZ LIKP0iWSdcrAxbpVgnOQc7iZIk5Oa0akLPzyik9CFOkr20bZJwq7sXuJl+Ujs+/bCV/S ekh/rmJp/NZKO/VO1OxHkv7vDharU+WOQmoBkvkw8iubFptnUN27wHN1xY4sXMfdm0CR T7DhTXzztK0DYJHYTkhSFV+lmugSzYxLY77oPezcNc67mV+EQV6McAP5zxOkN7UcGwxQ nBOZnNvV3DMxa21u/mkdQD1Mgt23PNnPS0gDmXcDYJs7SSyjJpgRr8lTEHZ7YMyBLkHy vwbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QpzOuiGn; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id t33si465347edb.339.2018.04.17.07.49.32; Tue, 17 Apr 2018 07:49:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QpzOuiGn; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 1880EC21D8E; Tue, 17 Apr 2018 14:48:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2C70FC21DFA; Tue, 17 Apr 2018 14:48:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 59097C21CB6; Tue, 17 Apr 2018 14:43:46 +0000 (UTC) Received: from mail-wr0-f195.google.com (mail-wr0-f195.google.com [209.85.128.195]) by lists.denx.de (Postfix) with ESMTPS id 77B9CC21BE5 for ; Tue, 17 Apr 2018 14:43:44 +0000 (UTC) Received: by mail-wr0-f195.google.com with SMTP id v60so32387453wrc.7 for ; Tue, 17 Apr 2018 07:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=6MiwNZNB2/R008cKl4zYWBY8FpHcUEB/jCTYz67hki8=; b=QpzOuiGny4KLEH5bxaa1HFkKqp+0nKbecfSFEt+UkHiAEZ+7zboEp9ZuGV9oDxqcGd ho5wPzgDvq3hItQHdU5HLmDnvJrFUyUnrgUSezBGjCPbBO90oLaz0PJrut+VwJZIKuaJ ztJYhZyYOgJUNso6+hnWpk7KpQaJopCZLIdyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=6MiwNZNB2/R008cKl4zYWBY8FpHcUEB/jCTYz67hki8=; b=SLgOU2A3PjVHl54MstYoLi0SatvaUbjTRCxzfqOYTUvGHLqWM+VE5pGA9MYBfyY6y0 IFuB0i9QtEkGUPqNYGU5lIJR8etQoCgkm7O82Ja+yKBaxokpJILEWhwaOxZ7e10yZo2R aGGiAWko9eVAwgkrpcqdnKE3nCRXmqR2KbEBZ1Dn0Ic2erTBgIBTildEWA7fCMFOhVpD goW7NKu7GuDrZV08ahbR7WSyb7VcwmBuI2D417OOY8U43dlBpGWbjIayX8PJK3cTWM1K AvTVU3cvwhb0D3gRmtS4OZyhkAI1GcAF7CQnJxQ48WBdp3DjEf4lcamk5jz5Eo/xQatL pF/g== X-Gm-Message-State: ALQs6tAP3AzRcoMbZw+j73pKi9YL0CRG3gjOAo8C6Sz0IfAaoKp9ZONm p0VPIgDjAM5jHgbSCluizapVHw== X-Received: by 10.80.176.36 with SMTP id i33mr3328006edd.252.1523976224095; Tue, 17 Apr 2018 07:43:44 -0700 (PDT) Received: from lx-rfried.mea.qualcomm.com ([185.23.60.4]) by smtp.gmail.com with ESMTPSA id j90sm8248231edb.12.2018.04.17.07.43.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 17 Apr 2018 07:43:43 -0700 (PDT) From: Ramon Fried To: mateusz.kulikowski@gmail.com, albert.u.boot@aribaud.net, jramirez@baylibre.com Date: Tue, 17 Apr 2018 17:43:37 +0300 Message-Id: <20180417144337.24482-1-ramon.fried@linaro.org> X-Mailer: git-send-email 2.15.1 X-Mailman-Approved-At: Tue, 17 Apr 2018 14:47:56 +0000 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] mach-snapdragon: Fix UART clock flow X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" UART clock enabling flow was wrong. Changed the flow according to downstream implementation in LK. Signed-off-by: Ramon Fried --- arch/arm/mach-snapdragon/clock-apq8016.c | 19 ++++++++++++------- arch/arm/mach-snapdragon/clock-apq8096.c | 4 ++-- arch/arm/mach-snapdragon/clock-snapdragon.c | 17 ++++++++++++++++- arch/arm/mach-snapdragon/clock-snapdragon.h | 9 +++++++-- .../arm/mach-snapdragon/include/mach/sysmap-apq8016.h | 1 + 5 files changed, 38 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c b/arch/arm/mach-snapdragon/clock-apq8016.c index a2424178c6..f3c486182f 100644 --- a/arch/arm/mach-snapdragon/clock-apq8016.c +++ b/arch/arm/mach-snapdragon/clock-apq8016.c @@ -18,7 +18,6 @@ /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) -#define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0) static const struct bcr_regs sdc_regs[] = { { @@ -37,11 +36,17 @@ static const struct bcr_regs sdc_regs[] = { } }; -static struct gpll0_ctrl gpll0_ctrl = { +static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, - .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, + .vote_bit = BIT(0), +}; + +static struct vote_clk gcc_blsp1_ahb_clk = { + .cbcr_reg = BLSP1_AHB_CBCR, + .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, + .vote_bit = BIT(10), }; /* SDHCI */ @@ -56,7 +61,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) /* 800Mhz/div, gpll0 */ clk_rcg_set_rate_mnd(priv->base, &sdc_regs[slot], div, 0, 0, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot)); return rate; @@ -73,12 +78,12 @@ static const struct bcr_regs uart2_regs = { /* UART: 115200 */ static int clk_init_uart(struct msm_clk_priv *priv) { - /* Enable iface clk */ - clk_enable_cbc(priv->base + BLSP1_AHB_CBCR); + /* Enable AHB clock */ + clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk); + /* 7372800 uart block clock @ GPLL0 */ clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 144, 15625, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); /* Enable core clk */ clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR); diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index 3d363d4d66..bc99572a4c 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -28,7 +28,7 @@ static const struct bcr_regs sdc_regs = { .D = SDCC2_D, }; -static const struct gpll0_ctrl gpll0_ctrl = { +static const struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -42,7 +42,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); return rate; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 899b5ba6ce..20902088f3 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -31,7 +31,7 @@ void clk_enable_cbc(phys_addr_t cbcr) ; } -void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0) +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0) { if (readl(base + gpll0->status) & gpll0->status_bit) return; /* clock already enabled */ @@ -42,6 +42,21 @@ void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *gpll0) ; } +#define BRANCH_ON_VAL (0) +#define BRANCH_NOC_FSM_ON_VAL BIT(29) +#define BRANCH_CHECK_MASK GENMASK(31, 28) + +void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk) +{ + u32 val; + + setbits_le32(base + vclk->ena_vote, vclk->vote_bit); + do { + val = readl(base + vclk->cbcr_reg); + val &= BRANCH_CHECK_MASK; + } while ((val != BRANCH_ON_VAL) && (val != BRANCH_NOC_FSM_ON_VAL)); +} + #define APPS_CMD_RGCR_UPDATE BIT(0) /* Update clock command via CMD_RGCR */ diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index d7026aa867..1023324e1a 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -12,13 +12,18 @@ #define CFG_CLK_SRC_GPLL0 (1 << 8) #define CFG_CLK_SRC_MASK (7 << 8) -struct gpll0_ctrl { +struct pll_vote_clk { uintptr_t status; int status_bit; uintptr_t ena_vote; int vote_bit; }; +struct vote_clk { + uintptr_t cbcr_reg; + uintptr_t ena_vote; + int vote_bit; +}; struct bcr_regs { uintptr_t cfg_rcgr; uintptr_t cmd_rcgr; @@ -31,7 +36,7 @@ struct msm_clk_priv { phys_addr_t base; }; -void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0); +void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); void clk_bcr_update(phys_addr_t apps_cmd_rgcr); void clk_enable_cbc(phys_addr_t cbcr); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h index 1094b14a80..2167fa0758 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8016.h @@ -14,6 +14,7 @@ /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) #define APCS_GPLL_ENA_VOTE (0x45000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) #define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004)