[v2,03/15] clk: imx7d: fix mipi dphy div parent

Message ID 20180423134750.30403-4-rui.silva@linaro.org
State Superseded
Headers show
Series
  • media: staging/imx7: add i.MX7 media driver
Related show

Commit Message

Rui Miguel Silva April 23, 2018, 1:47 p.m.
Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan
clock and set the correct parent.

before:
cat clk_orphan_summary
                                 enable  prepare  protect
   clock                          count    count    count        rate   accuracy   phase
----------------------------------------------------------------------------------------
 mipi_dphy_post_div                   1        1        0           0          0 0
    mipi_dphy_root_clk                1        1        0           0          0 0

cat clk_dump | grep mipi_dphy
mipi_dphy_post_div                    1        1        0           0          0 0
    mipi_dphy_root_clk                1        1        0           0          0 0

after:
cat clk_dump | grep mipi_dphy
   mipi_dphy_src                     1        1        0    24000000          0 0
       mipi_dphy_cg                  1        1        0    24000000          0 0
          mipi_dphy_pre_div          1        1        0    24000000          0 0
             mipi_dphy_post_div      1        1        0    24000000          0 0
                mipi_dphy_root_clk   1        1        0    24000000          0 0

Cc: linux-clk@vger.kernel.org
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>


Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>

---
 drivers/clk/imx/clk-imx7d.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.17.0

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Comments

Stephen Boyd May 1, 2018, 10:11 p.m. | #1
Quoting Rui Miguel Silva (2018-04-23 06:47:38)
> Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan

> clock and set the correct parent.

> 

> before:

> cat clk_orphan_summary

>                                  enable  prepare  protect

>    clock                          count    count    count        rate   accuracy   phase

> ----------------------------------------------------------------------------------------

>  mipi_dphy_post_div                   1        1        0           0          0 0

>     mipi_dphy_root_clk                1        1        0           0          0 0

> 

> cat clk_dump | grep mipi_dphy

> mipi_dphy_post_div                    1        1        0           0          0 0

>     mipi_dphy_root_clk                1        1        0           0          0 0

> 

> after:

> cat clk_dump | grep mipi_dphy

>    mipi_dphy_src                     1        1        0    24000000          0 0

>        mipi_dphy_cg                  1        1        0    24000000          0 0

>           mipi_dphy_pre_div          1        1        0    24000000          0 0

>              mipi_dphy_post_div      1        1        0    24000000          0 0

>                 mipi_dphy_root_clk   1        1        0    24000000          0 0

> 

> Cc: linux-clk@vger.kernel.org

> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>

> 

> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>


You have double signed-off-by here. Please resend.

Also, add a "Fixes:" tag so we know where to backport this to.

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Shawn Guo May 3, 2018, 1:08 a.m. | #2
Anson,

Please have a look at this change.

Shawn

On Mon, Apr 23, 2018 at 02:47:38PM +0100, Rui Miguel Silva wrote:
> Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove a orphan

> clock and set the correct parent.

> 

> before:

> cat clk_orphan_summary

>                                  enable  prepare  protect

>    clock                          count    count    count        rate   accuracy   phase

> ----------------------------------------------------------------------------------------

>  mipi_dphy_post_div                   1        1        0           0          0 0

>     mipi_dphy_root_clk                1        1        0           0          0 0

> 

> cat clk_dump | grep mipi_dphy

> mipi_dphy_post_div                    1        1        0           0          0 0

>     mipi_dphy_root_clk                1        1        0           0          0 0

> 

> after:

> cat clk_dump | grep mipi_dphy

>    mipi_dphy_src                     1        1        0    24000000          0 0

>        mipi_dphy_cg                  1        1        0    24000000          0 0

>           mipi_dphy_pre_div          1        1        0    24000000          0 0

>              mipi_dphy_post_div      1        1        0    24000000          0 0

>                 mipi_dphy_root_clk   1        1        0    24000000          0 0

> 

> Cc: linux-clk@vger.kernel.org

> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>

> 

> Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>

> ---

>  drivers/clk/imx/clk-imx7d.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

> 

> diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c

> index 975a20d3cc94..f7f4db2e6fa6 100644

> --- a/drivers/clk/imx/clk-imx7d.c

> +++ b/drivers/clk/imx/clk-imx7d.c

> @@ -729,7 +729,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)

>  	clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6);

>  	clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6);

>  	clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6);

> -	clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6);

> +	clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6);

>  	clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6);

>  	clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6);

>  	clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6);

> -- 

> 2.17.0

> 

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A.s. Dong May 3, 2018, 1:50 a.m. | #3
> -----Original Message-----

> From: Shawn Guo [mailto:shawnguo@kernel.org]

> Sent: Thursday, May 3, 2018 9:08 AM

> To: Rui Miguel Silva <rui.silva@linaro.org>; Anson Huang

> <anson.huang@nxp.com>

> Cc: mchehab@kernel.org; sakari.ailus@linux.intel.com; Steve Longerbeam

> <slongerbeam@gmail.com>; Philipp Zabel <p.zabel@pengutronix.de>; Rob

> Herring <robh+dt@kernel.org>; linux-media@vger.kernel.org;

> devel@driverdev.osuosl.org; Fabio Estevam <fabio.estevam@nxp.com>;

> devicetree@vger.kernel.org; Greg Kroah-Hartman

> <gregkh@linuxfoundation.org>; Ryan Harkin <ryan.harkin@linaro.org>;

> linux-clk@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>

> Subject: Re: [PATCH v2 03/15] clk: imx7d: fix mipi dphy div parent

> 

> Anson,

> 

> Please have a look at this change.

> 

> Shawn

> 

> On Mon, Apr 23, 2018 at 02:47:38PM +0100, Rui Miguel Silva wrote:

> > Fix the mipi dphy root divider to mipi_dphy_pre_div, this would remove

> > a orphan clock and set the correct parent.

> >

> > before:

> > cat clk_orphan_summary

> >                                  enable  prepare  protect

> >    clock                          count    count    count        rate   accuracy   phase

> > ----------------------------------------------------------------------------------------

> >  mipi_dphy_post_div                   1        1        0           0          0 0

> >     mipi_dphy_root_clk                1        1        0           0          0 0

> >

> > cat clk_dump | grep mipi_dphy

> > mipi_dphy_post_div                    1        1        0           0          0 0

> >     mipi_dphy_root_clk                1        1        0           0          0 0

> >

> > after:

> > cat clk_dump | grep mipi_dphy

> >    mipi_dphy_src                     1        1        0    24000000          0 0

> >        mipi_dphy_cg                  1        1        0    24000000          0 0

> >           mipi_dphy_pre_div          1        1        0    24000000          0 0

> >              mipi_dphy_post_div      1        1        0    24000000          0 0

> >                 mipi_dphy_root_clk   1        1        0    24000000          0 0

> >

> > Cc: linux-clk@vger.kernel.org

> > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>

> >

> > Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>


Two sign-off?

Otherwise, the patch looks ok to me.
Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>


Regards
Dong Aisheng

> > ---

> >  drivers/clk/imx/clk-imx7d.c | 2 +-

> >  1 file changed, 1 insertion(+), 1 deletion(-)

> >

> > diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c

> > index 975a20d3cc94..f7f4db2e6fa6 100644

> > --- a/drivers/clk/imx/clk-imx7d.c

> > +++ b/drivers/clk/imx/clk-imx7d.c

> > @@ -729,7 +729,7 @@ static void __init imx7d_clocks_init(struct

> device_node *ccm_node)

> >  	clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] =

> imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base +

> 0xa300, 0, 6);

> >  	clks[IMX7D_MIPI_DSI_ROOT_DIV] =

> imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0,

> 6);

> >  	clks[IMX7D_MIPI_CSI_ROOT_DIV] =

> imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0,

> 6);

> > -	clks[IMX7D_MIPI_DPHY_ROOT_DIV] =

> imx_clk_divider2("mipi_dphy_post_div", "mipi_csi_dphy_div", base +

> 0xa480, 0, 6);

> > +	clks[IMX7D_MIPI_DPHY_ROOT_DIV] =

> > +imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base +

> > +0xa480, 0, 6);

> >  	clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div",

> "sai1_pre_div", base + 0xa500, 0, 6);

> >  	clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div",

> "sai2_pre_div", base + 0xa580, 0, 6);

> >  	clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div",

> > "sai3_pre_div", base + 0xa600, 0, 6);

> > --

> > 2.17.0

> >

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Patch

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 975a20d3cc94..f7f4db2e6fa6 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -729,7 +729,7 @@  static void __init imx7d_clocks_init(struct device_node *ccm_node)
 	clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6);
 	clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6);
 	clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6);
-	clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_csi_dphy_div", base + 0xa480, 0, 6);
+	clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6);
 	clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6);
 	clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6);
 	clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6);