| Message ID | 20180425125449.19755-15-kishon@ti.com |
|---|---|
| State | Accepted |
| Commit | c29fd489118a2abd2d17c49ae980e3c67fa6d004 |
| Headers | show |
| Series | dra7: mmc: Update mmc dt node to use sdhci-omap | expand |
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ae2f8dd46328..90f378b28915 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1086,6 +1086,7 @@ status = "disabled"; pbias-supply = <&pbias_mmc_reg>; max-frequency = <192000000>; + mmc-ddr-1_8v; }; hdqw1w: 1w@480b2000 { @@ -1104,6 +1105,8 @@ max-frequency = <192000000>; /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ sdhci-caps-mask = <0x7 0x0>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; }; mmc3: mmc@480ad000 {
While the supported UHS mode can be obtained from CAPA2 register, SD Host Controller Standard Specification doesn't define bits for MMC's HS200 and DDR mode capability. Add properties to indicate MMC HS200 and DDR speed mode capability in dt node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm/boot/dts/dra7.dtsi | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html