From patchwork Fri Apr 27 00:38:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Katsuhiro Suzuki X-Patchwork-Id: 134544 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp96128lji; Thu, 26 Apr 2018 17:38:57 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpPtrQGK7tW/XYnnm5GzrVhZghJ463tzxyQpnHGq1BhlBm+Y9+ImVhYE2aeTCLMq/F7f386 X-Received: by 2002:a17:902:3c5:: with SMTP id d63-v6mr204444pld.163.1524789537480; Thu, 26 Apr 2018 17:38:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524789537; cv=none; d=google.com; s=arc-20160816; b=LfYvgC/ixHbJaBq4C4KtSyR3kdC++JvZBI3In+K8dP237R0D0T+EtoWu2glCb16tg7 eheGZFiZc8gsZePZr6btYqRBHR7SEqxHg15EzvmbZqYx1X0y4T/u1D0s7ynnKtD8ueuq EAbacikXcn1qZGb7dyBrbcCgIBfTCg3EOtBh2zjZlBMOxVHkmjr2wc6n5ztkipNe/lhq b+lnIAWZ3bhlwRC8liKG9rmMOGh/0sWmS+0FjJtvwdoq8iZMDM+RF8xPVXPQ5LpU+AQa mX6zF7XmaO8a4PK8k/MNPZEnC+tBg9rZY6Erq+D8ZC3USbBa6Tp8UK5sgmNLV/pBaON3 Zctg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=XsHt5MJfP+elW6DyvQ3BL9WSgjphxNlhrHiielYeems=; b=BbISxoxHkjVGLKEKkY3LsG0er57VphbP1hKrlsc59P2Zi+GkC7UvCpc/786+2eo28Y ZJZvNOn/lGkoIB/WB210QGqn+8HYxxF1h70AlWziYwPYrIF7XP+k80xQzdGLrinpJWip HRLMujCgwtMXaInPdtTVlY+Jcq2eNxTZte6YUIKcaMoBhXF8n3q3Fu0Pd9lrLlvXaET+ bAajEd8ddOLy/cXGRJmyOWOXhCcmuftD8ZMN6WMasUgU5bh0IVEvUG+lsnyRI088LqV3 OQ7ta7crSKM8Cdg24svwSliz2MKNV5thOy/XPvuMPZtG3ek1k0cFJdEEWn9kJlelyQ5f FLcg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t4-v6si92905pgr.457.2018.04.26.17.38.56; Thu, 26 Apr 2018 17:38:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754728AbeD0Ai4 (ORCPT + 5 others); Thu, 26 Apr 2018 20:38:56 -0400 Received: from mx.socionext.com ([202.248.49.38]:11177 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752358AbeD0Aiz (ORCPT ); Thu, 26 Apr 2018 20:38:55 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 27 Apr 2018 09:38:53 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id D9DDD6007A; Fri, 27 Apr 2018 09:38:53 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 27 Apr 2018 09:38:53 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id B81EF1A01BC; Fri, 27 Apr 2018 09:38:53 +0900 (JST) Received: from aegis.e01.socionext.com (unknown [10.213.134.210]) by yuzu.css.socionext.com (Postfix) with ESMTP id 8D61E120133; Fri, 27 Apr 2018 09:38:53 +0900 (JST) From: Katsuhiro Suzuki To: linux-gpio@vger.kernel.org, Linus Walleij , Masahiro Yamada , linux-arm-kernel@lists.infradead.org Cc: Masami Hiramatsu , Jassi Brar , linux-kernel@vger.kernel.org, Katsuhiro Suzuki Subject: [PATCH 1/2] pinctrl: uniphier: add LD20 MPEG2-TS I/O pin-mux settings Date: Fri, 27 Apr 2018 09:38:43 +0900 Message-Id: <20180427003844.3937-1-suzuki.katsuhiro@socionext.com> X-Mailer: git-send-email 2.17.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The MPEG2-TS input/output core both accepts serial TS and parallel TS. The serial TS interface uses following pins: hscin0_s : HS0DOUT[0-3] hscin1_s : HS0DOUT[4-7] hscin2_s : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN0 hscin3_s : HS1DIN[2-5] hscout0_s: HS0DOUT[0-3] hscout1_s: HS0DOUT[4-7] And the parallel TS interface uses following pins: hscin0_p : HS0BCLKIN, HS0SYNCIN, HS0VALIN, HS0DIN[0-7] hscin1_p : HS1BCLKIN, HS1SYNCIN, HS1VALIN, HS1DIN[0-7] hscout0_p: HS0BCLKOUT, HS0SYNCOUT, HS0VALOUT, HS0DOUT[0-7] Signed-off-by: Katsuhiro Suzuki --- .../pinctrl/uniphier/pinctrl-uniphier-ld20.c | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) -- 2.17.0 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index bf8f0c3bea5e..6528c13ea4bd 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -566,6 +566,33 @@ static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39, 41, 42, 45}; static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1}; +static const unsigned hscin0_ci_pins[] = {102, 103, 104, 105, 106, 107, 108, + 109, 110, 111, 112}; +static const int hscin0_ci_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +static const unsigned hscin0_p_pins[] = {102, 103, 104, 105, 106, 107, 108, 109, + 110, 111, 112}; +static const int hscin0_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned hscin1_p_pins[] = {124, 125, 126, 127, 128, 129, 130, 131, + 132, 133, 134}; +static const int hscin1_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned hscin0_s_pins[] = {116, 117, 118, 119}; +static const int hscin0_s_muxvals[] = {3, 3, 3, 3}; +static const unsigned hscin1_s_pins[] = {120, 121, 122, 123}; +static const int hscin1_s_muxvals[] = {3, 3, 3, 3}; +static const unsigned hscin2_s_pins[] = {124, 125, 126, 127}; +static const int hscin2_s_muxvals[] = {3, 3, 3, 3}; +static const unsigned hscin3_s_pins[] = {129, 130, 131, 132}; +static const int hscin3_s_muxvals[] = {3, 3, 3, 3}; +static const unsigned hscout0_ci_pins[] = {113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123}; +static const int hscout0_ci_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; +static const unsigned hscout0_p_pins[] = {113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123}; +static const int hscout0_p_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; +static const unsigned hscout0_s_pins[] = {116, 117, 118, 119}; +static const int hscout0_s_muxvals[] = {4, 4, 4, 4}; +static const unsigned hscout1_s_pins[] = {120, 121, 122, 123}; +static const int hscout1_s_muxvals[] = {4, 4, 4, 4}; static const unsigned i2c0_pins[] = {63, 64}; static const int i2c0_muxvals[] = {0, 0}; static const unsigned i2c1_pins[] = {65, 66}; @@ -641,6 +668,17 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(ether_rgmii), UNIPHIER_PINCTRL_GROUP(ether_rmii), + UNIPHIER_PINCTRL_GROUP(hscin0_ci), + UNIPHIER_PINCTRL_GROUP(hscin0_p), + UNIPHIER_PINCTRL_GROUP(hscin1_p), + UNIPHIER_PINCTRL_GROUP(hscin0_s), + UNIPHIER_PINCTRL_GROUP(hscin1_s), + UNIPHIER_PINCTRL_GROUP(hscin2_s), + UNIPHIER_PINCTRL_GROUP(hscin3_s), + UNIPHIER_PINCTRL_GROUP(hscout0_ci), + UNIPHIER_PINCTRL_GROUP(hscout0_p), + UNIPHIER_PINCTRL_GROUP(hscout0_s), + UNIPHIER_PINCTRL_GROUP(hscout1_s), UNIPHIER_PINCTRL_GROUP(i2c0), UNIPHIER_PINCTRL_GROUP(i2c1), UNIPHIER_PINCTRL_GROUP(i2c3), @@ -668,6 +706,16 @@ static const char * const aoutiec1_groups[] = {"aoutiec1"}; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; static const char * const ether_rgmii_groups[] = {"ether_rgmii"}; static const char * const ether_rmii_groups[] = {"ether_rmii"}; +static const char * const hscin0_groups[] = {"hscin0_s", + "hscin0_p", + "hscout0_ci"}; +static const char * const hscin1_groups[] = {"hscin1_s", "hscin0_p"}; +static const char * const hscin2_groups[] = {"hscin2_s"}; +static const char * const hscin3_groups[] = {"hscin3_s"}; +static const char * const hscout0_groups[] = {"hscout0_s", + "hscout0_p", + "hscout0_ci"}; +static const char * const hscout1_groups[] = {"hscout1_s"}; static const char * const i2c0_groups[] = {"i2c0"}; static const char * const i2c1_groups[] = {"i2c1"}; static const char * const i2c3_groups[] = {"i2c3"}; @@ -691,6 +739,12 @@ static const struct uniphier_pinmux_function uniphier_ld20_functions[] = { UNIPHIER_PINMUX_FUNCTION(emmc), UNIPHIER_PINMUX_FUNCTION(ether_rgmii), UNIPHIER_PINMUX_FUNCTION(ether_rmii), + UNIPHIER_PINMUX_FUNCTION(hscin0), + UNIPHIER_PINMUX_FUNCTION(hscin1), + UNIPHIER_PINMUX_FUNCTION(hscin2), + UNIPHIER_PINMUX_FUNCTION(hscin3), + UNIPHIER_PINMUX_FUNCTION(hscout0), + UNIPHIER_PINMUX_FUNCTION(hscout1), UNIPHIER_PINMUX_FUNCTION(i2c0), UNIPHIER_PINMUX_FUNCTION(i2c1), UNIPHIER_PINMUX_FUNCTION(i2c3),