From patchwork Tue May 1 08:59:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134740 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4726988lji; Tue, 1 May 2018 01:59:44 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpy4V7jHfETX8Wc2apTdfDhXy8lv9wpqk9Hbp0EhoYpVPIDRLJx+YHBeaiE0Ju16FqQy/1u X-Received: by 2002:adf:a925:: with SMTP id u34-v6mr12282603wrc.248.1525165183960; Tue, 01 May 2018 01:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165183; cv=none; d=google.com; s=arc-20160816; b=TrX7UXrMh48lUGrIjU6MGrSwk7hwMqJliT/SO0zq2AIz4C/FzGaG7YhxwFILV0coue O8QoQlHn1JLxgG8RoCLE2TpzADflOyA2ip81STvwDm5YmcSC3Uwms7DnpZ8258rcl/5I 6OKPlcBN7htrd76G+rHCHHXtJ17O3eoHcDtH/A4aRMY40Efq18ITxdinmol9FHPsEE5R PjmcN76ly/gNhXFLKzpM3XW730nn+jQ03eZHIPF45WLsM1f3M6cFZr6LCzcGB9LTJRSe kTFo5AWrudFSltxArZ4jKFYkV7LUZt6MiXyykTvsGp0dOEbiQzpeMiqucSz/Y9a5XrRA 3mJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=UeZPkjdD16azuUGTRiQQEzGOX/XB9yhOSpriy/STCD0=; b=Q7tfZEwoKsni+SX3zBq2EKr2OwmQ8PksDZdsqykO6/pRp+sFdu7tAqqlKE1IxMHr1M Hix4KWgoQ6bXvEdSUZjNXemX/MUHLBFM4239U1jD8zFQuaVOjqDiS4JMJt8Fogi1Hxf9 02ZMDYz8064249yTO/NMqUFrREYD4dJBk/i+VLC3ZOSi7+tdyd7tJAYtXpFQIfDZ/adF YEYhmwNAW9txxFfLs2H7nQ/r6R88d+Xbi+4oPq9tXttNunHcfd3SnC8No6A7gcOT1ULY wgO9kR1cawTo6+GVBKnYEBlwZ3Sb1vb5eGYaiuOENrLAAOm0MRb0LfitzYEQtYXGNfBb bWiQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id v195si6728417wmd.60.2018.05.01.01.59.43 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8R-0007Ma-EM; Tue, 01 May 2018 09:59:43 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 04/12] Make address_space_access_valid() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:31 +0100 Message-Id: <20180501085939.6201-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_access_valid(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- include/exec/memory.h | 4 +++- include/sysemu/dma.h | 3 ++- exec.c | 3 ++- target/s390x/diag.c | 6 ++++-- target/s390x/excp_helper.c | 3 ++- target/s390x/mmu_helper.c | 3 ++- target/s390x/sigp.c | 3 ++- 7 files changed, 17 insertions(+), 8 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index 1af4e3cd5b..eb1ceace27 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1938,8 +1938,10 @@ static inline MemoryRegion *address_space_translate(AddressSpace *as, * @addr: address within that address space * @len: length of the area to be checked * @is_write: indicates the transfer direction + * @attrs: memory attributes */ -bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write); +bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, + bool is_write, MemTxAttrs attrs); /* address_space_map: map a physical memory region into a host virtual address * diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index 0d73902634..5da3c4e3c5 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -77,7 +77,8 @@ static inline bool dma_memory_valid(AddressSpace *as, DMADirection dir) { return address_space_access_valid(as, addr, len, - dir == DMA_DIRECTION_FROM_DEVICE); + dir == DMA_DIRECTION_FROM_DEVICE, + MEMTXATTRS_UNSPECIFIED); } static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, diff --git a/exec.c b/exec.c index eb6471abfe..87650dc7ed 100644 --- a/exec.c +++ b/exec.c @@ -3445,7 +3445,8 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, } bool address_space_access_valid(AddressSpace *as, hwaddr addr, - int len, bool is_write) + int len, bool is_write, + MemTxAttrs attrs) { FlatView *fv; bool result; diff --git a/target/s390x/diag.c b/target/s390x/diag.c index a755837ad5..6ab473e7b6 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -140,7 +140,8 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra) return; } if (!address_space_access_valid(&address_space_memory, addr, - sizeof(IplParameterBlock), false)) { + sizeof(IplParameterBlock), false, + MEMTXATTRS_UNSPECIFIED)) { s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra); return; } @@ -169,7 +170,8 @@ out: return; } if (!address_space_access_valid(&address_space_memory, addr, - sizeof(IplParameterBlock), true)) { + sizeof(IplParameterBlock), true, + MEMTXATTRS_UNSPECIFIED)) { s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra); return; } diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index dfee221111..f0ce60cff2 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -120,7 +120,8 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, /* check out of RAM access */ if (!address_space_access_valid(&address_space_memory, raddr, - TARGET_PAGE_SIZE, rw)) { + TARGET_PAGE_SIZE, rw, + MEMTXATTRS_UNSPECIFIED)) { DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, (uint64_t)raddr, (uint64_t)ram_size); trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index a25deef5dd..145b62a7ef 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -461,7 +461,8 @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages, return ret; } if (!address_space_access_valid(&address_space_memory, pages[i], - TARGET_PAGE_SIZE, is_write)) { + TARGET_PAGE_SIZE, is_write, + MEMTXATTRS_UNSPECIFIED)) { trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0); return -EFAULT; } diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index aff1530c82..c1f9245797 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -280,7 +280,8 @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg) cpu_synchronize_state(cs); if (!address_space_access_valid(&address_space_memory, addr, - sizeof(struct LowCore), false)) { + sizeof(struct LowCore), false, + MEMTXATTRS_UNSPECIFIED)) { set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER); return; }